參數(shù)資料
型號(hào)： ORSO82G5-2FN680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 142/153頁
文件大?。?/td> 0K
描述： IC TRANCEIVERS FPSC 680FPBGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
89
30A03
[0]
NO_TX_RDI_EXSEQ
00
Not Transmission of RDI, If
NO_TX_RDI_EXSEQ = 1, a transmit link will
not send data if its corresponding receive link is
not good due to excessive sequence errors. If
this bit is set to 0, a transmit link will still send
data even if its corresponding receive link has
excessive sequence errors. This bit should
always be set during simulation and in SONET
mode.
Both
[1]
AUTO_BUNDLE
Automatic (Link) Bundle, AUTO_BUNDLE = 1
allows a link within a link group to remain active
even when another link within that group is
defective. Cell data from all links within that
group will continue to be sent to the FPGA. If
this bit is set to 0, then all links within a link
group must be good before cell data are read
from the links by the IPC and passed to the
FPGA.
Cell
[2]
RSVD
Reserved
—
[3]
REJOIN_A
Link Rejoin, REJOIN = 1 forces any link in a
SERDES block to reassert a “RX link good” sig-
nal automatically when three consecutive
sequence numbers are correct on that link.
Cell
[4]
AUTO_REMOVE_A
Automatic (Link) Remove, AUTO_REMOVE = 1
indicates that any link in a SERDES block which
sees three excessive sequence errors should
deassert the “RX link good” signal which will
cause the link to be inactive.
Cell
[5]
RSVD
Reserved
[6]
REJOIN_B
Link Rejoin, REJOIN = 1 forces any link in a
SERDES block to reassert a “RX link good” sig-
nal automatically when three consecutive
sequence numbers are correct on that link.
Cell
[7]
AUTO_REMOVE_B
AUTO_REMOVE_B = 1 indicates that any link in
SERDES block B which sees three excessive
sequence errors should deassert the “RX link
good” signal which will cause the link to be inac-
tive.
Cell
30A04
[0:1]
RSVD
00
Reserved
—
[2]
FMPU_RESYNC2_B2
Control to resync channels BC and BD which
have been congured for multi channel align-
ment in SONET mode in block B. Requires a ris-
ing edge on this bit. Write a 0 followed by a 1.
SONET
[3:4]
RSVD
Reserve
SONET
[5]
FMPU_RESYNC2_A2
Control to resync channels AC and AD which
have been congured for multi channel align-
ment in SONET mode in block A. Requires a
rising edge on this bit. Write a 0 followed by a 1.
SONET
[6]
RSVD
Reserved
SONET
[7]
FMPU_RESYNC4
Control to resync all four channels which have
been congured for multi channel alignment.
SONET
Table 28. Common Control Register Descriptions – ORSO42G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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參數(shù)描述
ORSO82G5-2FN680C1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7 Gb Bp ln Xcvr 643K Gt I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-2FN680I1 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO82G5-3F680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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