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| 型號： | OR2T04A5J160-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 100 CLBS, 4800 GATES, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 163/196頁 |
| 文件大?。?/td> | 3475K |
| 代理商： | OR2T04A5J160-DB |
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Data Sheet
January 2003
ORCA Series 2 FPGAs
Lattice Semiconductor
69
Special-Purpose Pins Special-Purpose Pins (Become User I/O After Conguration) (continued)
M0, M1, M2
I
During powerup and initialization, M0—M2 are used to select the conguration mode
with their values latched on the rising edge of INIT. See Table 7 for the conguration
modes. During conguration, a pull-up is enabled, and after conguration, the pins are
user-programmable I/O*.
M3
I
During powerup and initialization, M3 is used to select the speed of the internal oscilla-
tor during conguration, with its value latched on the rising edge of INIT. When M3 is
low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz.
During conguration, a pull-up is enabled, and after conguration, this pin is a user-pro-
grammable I/O pin*.
TDI, TCK, TMS
I
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited once
conguration is complete, and these pins are user-programmable I/O pins. Even if
boundary scan is not used, either TCK or TMS must be held at logic 1 during congura-
tion. Each pin has a pull-up enabled during conguration*.
HDC
O
High During Conguration is output high until conguration is complete. It is used as a
control output indicating that conguration is not complete. After conguration, this pin
is a user-programmable I/O pin*.
LDC
OLow During Conguration is output low until conguration is complete. It is used as a
control output indicating that conguration is not complete. After conguration, this pin
is a user-programmable I/O pin*.
INIT
I/O
INIT is a bidirectional signal before and during conguration. During conguration, a
pull-up is enabled, but an external pull-up resistor is recommended. As an active-low
open-drain output, INIT is held low during power stabilization and internal clearing of
memory. As an active-low input, INIT holds the FPGA in the wait-state before the start
of conguration. After conguration, the pin is a user-programmable I/O pin*.
CS0, CS1, WR, RD
I
CS0, CS1, WR, RD are used in the asynchronous peripheral conguration modes. The
FPGA is selected when CS0 is low and CS1 is high. When selected, a low on the write
strobe, WR, loads the data on D[7:0] inputs into an internal data buffer. WR, CS0, and
CS1 are also used as chip selects in the slave parallel mode.
A low on RD changes D7 into a status output. As a status indication, a high indicates
ready and a low indicates busy. WR and RD should not be used simultaneously. If they
are, the write strobe overrides. During conguration, a pull-up is enabled, and after con-
guration, the pins are user-programmable I/O pins*.
A[17:0]
O
During master parallel conguration mode, A[17:0] address the conguration EPROM.
During conguration, a pull-up is enabled, and after conguration, the pins are user-
programmable I/O pins*.
D[7:0]
I
During master parallel, peripheral, and slave parallel conguration modes, D[7:0]
receive conguration data and each pin has a pull-up enabled. After conguration, the
pins are user-programmable I/O pins*.
DOUT
O
During conguration, DOUT is the serial data output that can drive the DIN of daisy-
chained slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After conguration, DOUT is a user-programmable I/O pin*.
Table 17. Pin Descriptions (continued)
Symbol
I/O
Description
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other conguration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
Pin Information (continued)
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