參數(shù)資料
型號(hào)： OR2T04A5J160-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 100 CLBS, 4800 GATES, PQFP160
封裝： QFP-160
文件頁數(shù)： 141/196頁
文件大?。?/td> 3475K
代理商： OR2T04A5J160-DB
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Lattice Semiconductor
49
Data Sheet
January 2003
ORCA Series 2 FPGAs
Bit Stream Error Checking
There are three different types of bit stream error
checking performed in the ORCA Series 2 FPGAs:
ID frame, frame alignment, and parity checking.
An optional ID data frame can be sent to a specied
address in the FPGA. This ID frame contains a unique
code for the part it was generated for which is com-
pared within the FPGA. Any differences are agged as
an ID error. This frame is automatically created by the
bit stream generation program in ORCA Foundry.
Every data frame in the FPGA begins with a start bit
set to 0 and three or more stop bits set to 1. If any of
the three previous bits were a 0 when a start bit is
encountered, it is agged as a frame alignment error.
Parity checking is also done on the FPGA for each
frame, if it has been enabled by setting the prty_en bit
to 1 in the ID frame. This is set by enabling the parity
check option in the bit stream generation program of
ORCA Foundry. Two parity bits, opar and epar, are
used to check the parity of bits in alternating bit posi-
tions to even parity in each data frame. If an odd num-
ber of ones is found for either the even bits (starting
with the start bit) or the odd bits (starting with the pro-
gram bit), then a parity error is agged.
When any of the three possible errors occur, the FPGA
is forced into the INIT state, forcing INIT low. The FPGA
will remain in this state until either the RESET or PRGM
pins are asserted.
FPGA Conguration Modes
There are eight methods for conguring the FPGA.
Seven of the conguration modes are selected on the
M0, M1, and M2 inputs. The eighth conguration mode
is accessed through the boundary-scan interface. A
fourth input, M3, is used to select the frequency of the
internal oscillator, which is the source for CCLK in
some conguration modes. The nominal frequencies of
the internal oscillator are 1.25 MHz and 10 MHz. The
1.25 MHz frequency is selected when the M3 input is
unconnected or driven to a high state.
There are three basic FPGA conguration modes:
master, slave, and peripheral. The conguration data
can be transmitted to the FPGA serially or in parallel
bytes. As a master, the FPGA provides the control sig-
nals out to strobe data in. As a slave device, a clock is
generated externally and provided into CCLK. In the
peripheral mode, the FPGA acts as a microprocessor
peripheral. Table 10 lists the functions of the congura-
tion mode pins.
Table 10. Conguration Modes
Master Parallel Mode
The master parallel conguration mode is generally
used to interface to industry-standard byte-wide mem-
ory, such as the 2764 and larger EPROMs. Figure 40
provides the connections for master parallel mode. The
FPGA outputs an 18-bit address on A[17:0] to memory
and reads one byte of conguration data on the rising
edge of RCLK. The parallel bytes are internally serial-
ized starting with the least signicant bit, D0.
5-4483(F)
Figure 40. Master Parallel Conguration Schematic
There are two parallel master modes: master up and
master down. In master up, the starting memory
address is 00000 Hex and the FPGA increments the
address for each byte loaded. In master down, the
starting memory address is 3FFFF Hex and the FPGA
decrements the address.
One master mode FPGA can interface to the memory
and provide conguration data on DOUT to additional
FPGAs in a daisy chain. The conguration data on
DOUT is provided synchronously with the falling edge
of CCLK. The frequency of the CCLK output is eight
times that of RCLK.
M2
M1
M0
CCLK
Conguration
Mode
Data
000
Output
Master
Serial
001
Input
Slave Parallel
Parallel
010
Reserved
011
Input
Sync Peripheral
Parallel
100
Output
Master (up)
Parallel
101
Output
Async Peripheral
Parallel
110
Output
Master (down)
Parallel
111
Input
Slave
Serial
TO DAISY-
CHAINED
DEVICES
DOUT
CCLK
HDC
LDC
RCLK
A[17:0]
D[7:0]
DONE
PRGM
M2
M1
M0
A[17:0]
D[7:0]
OE
CE
PROGRAM
VDD
VDD OR GND
EPROM
ORCA
SERIES
FPGA
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