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參數(shù)資料
| 型號： | OM4085T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PDSO40 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 225K |
| 代理商： | OM4085T |
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1997 Feb 25
21
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
OM4085
Table 7
LCD bias configuration
Table 8
Display status
Table 9
Power dissipation mode
Table 10
Load data pointer
Table 11
Device select
Table 12
Input bank selection
Table 13
Output bank selection
Table 14
Blinking frequency
LCD BIAS
BIT B
1
3
bias
1
2
bias
0
1
DISPLAY STATUS
BIT E
Disabled (blank)
Enabled
0
1
MODE
BIT LP
Normal mode
Power-saving mode
0
1
BITS
P4
P3
P2
P1
P0
5-bit binary value of 0 to 23
BITS
A0
A1
A2
3-bit binary value of 0 to 7
STATIC
1 : 2 MUX
BIT 1
RAM bit 0
RAM bit 2
RAM bits 0, 1
RAM bits 2, 3
0
1
STATIC
1 : 2 MUX
BIT 0
RAM bit 0
RAM bit 2
RAM bits 0, 1
RAM bits 2, 3
0
1
BLINK
FREQUENCY
BIT BF1
BIT BF0
Off
2 Hz
1 Hz
0.5 Hz
0
0
1
1
0
1
0
1
Table 15
Blink mode selection
Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the OM4085 and coordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
Cascaded operation
In large display configurations, up to 16 OM4085s can be
distinguished on the same I
2
C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I
2
C-bus slave address (SA0). It is also
possible to cascade up to 16 OM4085s. When cascaded,
several OM4085s are synchronized so that they can share
the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the outputs of only one device
need to be through-plated to the backplane electrodes of
the display. The other OM4085s of the cascade contribute
additional segment outputs but their backplane outputs are
left open-circuit (Fig.17).
The SYNC line is provided to maintain the correct
synchronization between all cascaded OM4085s.
This synchronization is guaranteed after the power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when OM4085s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output section being realized as an open-drain driver
with an internal pull-up resistor. A OM4085 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be
restored by the first OM4085 to assert SYNC. The timing
relationships between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.18. The waveforms are identical with the
parent device PCF8576. Cascade ability between
OM4085s and PCF8576s is possible, giving cost effective
LCD applications.
BLINK MODE
BIT A
Normal blinking
Alternation blinking
0
1
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