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參數(shù)資料
| 型號： | OM4085T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅動器 |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PDSO40 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大小： | 225K |
| 代理商： | OM4085T |
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1997 Feb 25
12
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
OM4085
Oscillator
The internal logic and the LCD drive signals of the
OM4085 or PCF8576 are timed either by the built-in
oscillator or from an external clock.
The clock frequency (f
CLK
) determines the LCD frame
frequency and the maximum rate for data reception from
the I
2
C-bus. To allow I
2
C-bus transmissions at their
maximum data rate of 100 kHz, f
CLK
should be chosen to
be above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
Internal clock
When the internal oscillator is used, OSC (pin 6) should be
tied to V
SS
. In this case, the output from CLK (pin 4)
provides the clock signal for cascaded OM4085s and
PCF8576s in the system.
External clock
The condition for external clock is made by tying OSC
(pin 6) to V
DD
; CLK (pin 4) then becomes the external
clock input.
Timing
The timing of the OM4085 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the OM4085s in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (Table 3). The frame
frequency is set by MODE SET commands when internal
clock is used, or by the frequency applied to pin 4 when
external clock is used.
Table 3
LCD frame frequencies
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
OM4085 MODE
f
frame
NOMINAL
f
frame
(Hz)
64
64
Normal mode
Power saving mode
f
CLK
/2880
f
CLK
/480
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I
2
C-bus. When a
device is unable to ‘digest’ a display data byte before the
next one arrives, it holds the SCL line LOW until the first
display data byte is stored. This slows down the
transmission rate of the I
2
C-bus but no data loss occurs.
Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data are displayed.
Segment outputs
The LCD drive section includes 24 segment outputs
S0 to S23 (pins 17 to 40) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with the data resident in the display latch.
When less than 24 segment outputs are required the
unused segment outputs should be left open-circuit.
Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open. In the 1 : 3 multiplex drive mode BP3
carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode
BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
Display RAM
The display RAM is a static 24
×
4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the ‘on’
state of the corresponding LCD segment; similarly, a
logic 0 indicates the ‘off’ state.
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