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參數(shù)資料
| 型號(hào)： | OM4085T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | Universal LCD driver for low multiplex rates |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, PDSO40 |
| 文件頁(yè)數(shù)： | 20/36頁(yè) |
| 文件大?。?/td> | 225K |
| 代理商： | OM4085T |
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1997 Feb 25
20
Philips Semiconductors
Product specification
Universal LCD driver for low multiplex
rates
OM4085
Table 5
Definition of OM4085 commands
Table 6
LCD drive mode
COMMAND/OPCODE
OPTIONS
DESCRIPTION
Mode set
C
1
0
LP
E
B
M1
M0
see Table 6
see Table 7
see Table 8
defines LCD drive mode
defines LCD bias configuration
defines display status; the possibility to disable
the display allows implementation of blinking
under external control
defines power dissipation mode
see Table 9
Load data pointer
C
0
0
P4
P3
P2
P1
P0
see Table 10
five bits of immediate data, bits P4 to P0, are
transferred to the data pointer to define one of
twenty-four display RAM addresses
Device select
C
1
1
0
0
A2
A1
A0
see Table 11
three bits of immediate data, bits A0 to A2, are
transferred to the subaddress counter to define
one of eight hardware subaddresses
Bank select
C
1
1
1
1
0
I
O
see Table 12
defines input bank selection (storage of arriving
display data)
defines output bank selection (retrieval of LCD
display data)
the BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes
see Table 13
Blink
C
1
1
1
0
A
BF1 BF0
see Table 14
see Table 15
defines the blinking frequency
selects the blinking mode; normal operation
with frequency set by bits BF1 and BF0, or
blinking by alternation of display RAM banks.
Alternation blinking does not apply in 1 : 3 and
1 : 4 multiplex drive modes
LCD DRIVE MODE
BIT M1
BIT M0
Static (1 BP)
1 : 2 MUX (2 BP)
1 : 3 MUX (3 BP)
1 : 4 MUX (4 BP)
0
1
1
0
1
0
1
0
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