參數(shù)資料
型號: OM4031T
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號處理外設(shè)
英文描述: Digital post-detection filter for FSK data receivers
中文描述: 1-BIT, DSP-DIGITAL FILTER, PDSO8
封裝: 3.90 MM, PLASTIC, SOT-96-1, SOP-8
文件頁數(shù): 8/16頁
文件大小: 68K
代理商: OM4031T
October 1994
8
Philips Semiconductors
Preliminary specification
Digital post-detection filter
for FSK data receivers
OM4031T
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
DC CHARACTERISTICS
V
DD
= 1.8 to 6.0 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
Notes
1.
V
DD
= 2.0 V; V
IL
= V
SS
; V
IH
= V
DD
; DOUT is open-circuit; clock signal at input CLK; f
clk
= 38.4 kHz, amplitude:
V
SS
to V
DD
; data signal at input DIN: random pattern at 20 kHz to simulate 2400 bits/s data with noise; t
r
= t
f
= 5 ns.
The operating current will be higher than specified when the input signal amplitude is less than 100%
(equals V
SS
to V
DD
) or when longer rise/fall times are used. This is caused by the Schmitt-trigger circuits drawing
extra current.
2.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
V
DD
V
I
I
I
I
O
P
tot
T
amb
T
stg
supply voltage
input voltage on any pin
DC input current all pins
DC output current all pins
total power dissipation
operating ambient temperature
storage temperature
0.5
0.5
10
55
7.0
V
DD
+ 0.5
20
20
150
+70
+125
V
V
mA
mA
mW
°
C
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DD
I
DDPD
I
DD
supply voltage
power-down supply voltage
operating supply current
1.8
1.0
1.5
6.0
10.0
20.0
V
μ
A
μ
A
CE = V
SS
; note 1
CE = V
DD
; notes 1 and 2
Inputs A0, A1, CLK and CE
V
IL
V
IH
I
LI
C
I
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance
0.5
0.7V
DD
2.0
+0.3V
DD
V
DD
+ 0.5 V
1.0
V
V
I
= V
DD
or V
I
= V
SS
tested on sample basis
μ
A
pF
Output DOUT
I
OL
I
LO
LOW level output current
output leakage current
V
OL
= 0.4 V
V
OH
= V
DD
1.0
1.0
mA
μ
A
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