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參數(shù)資料
| 型號(hào)： | OM4031T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Digital post-detection filter for FSK data receivers |
| 中文描述： | 1-BIT, DSP-DIGITAL FILTER, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, SOT-96-1, SOP-8 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | OM4031T |
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October 1994
7
Philips Semiconductors
Preliminary specification
Digital post-detection filter
for FSK data receivers
OM4031T
OPERATING INSTRUCTIONS
Control signals
The operation of the OM4031T is determined by 3 control
signals (CE, A0 and A1) and the clock frequency at input
CLK. Table 1 shows the various possibilities for a typical
clock frequency of 38.4 kHz.
The parameter N is the number of samples used in the
calculation of the average bit value.
The parameter f
s
is the input sampling frequency,
assuming a 38.4 kHz external clock signal.
The logic levels on A0 and A1 can be changed while
CE = HIGH, except to select or deselect 2400 bits/s with
doubled bandwidth (A1 = LOW, A0 = HIGH). This mode
must be entered or left while CE = LOW to avoid data
errors on DOUT.
Table 1
Data rate and filter bandwidth selection
Note
1.
At 4800 bits/s the oversampling rate is 8.
CE
A1
A0
N
(samples)
f
s
(kHz)
DATA RATE (bits/s)
NORMAL
BANDWIDTH
DOUBLE
BANDWIDTH
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
X
12
12
6
12
X
X
X
9.6
19.2
38.4
38.4
600
1200
4800
(1)
2400
600
2400
1200
Power-down mode
To reduce power consumption the filter can be disabled by
applying a LOW level to input CE. The result is as follows:
The internal clock is inhibited
Output DOUT is made 3-state and static.
Reset
The OM4031T is reset internally when power-down mode
is left by applying a HIGH level to input CE. The actual
reset takes place on the second falling edge on input CLK
after CE = HIGH.
The status after reset is as follows:
The shift register contains a 101010... pattern
DOUT is made LOW.
After power-up input CE must be kept at a LOW level for
at least one clock period on input CLK. This ensures a
successful reset when CE is made HIGH.
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