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參數(shù)資料
| 型號(hào)： | OM4031T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Digital post-detection filter for FSK data receivers |
| 中文描述： | 1-BIT, DSP-DIGITAL FILTER, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, SOT-96-1, SOP-8 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 68K |
| 代理商： | OM4031T |
October 1994
2
Philips Semiconductors
Preliminary specification
Digital post-detection filter
for FSK data receivers
OM4031T
FEATURES
External clock frequency 30 to 80 kHz (typ. 38.4 kHz)
Supported data rates 600, 1200, 2400 and 4800 bits/s
(typ.)
Double bandwidth option (not for 4800 bits/s)
Schmitt-triggered inputs for optimum slope tolerance
Enable input for power-down mode
Open-drain output (3-state in power-down mode)
No external components required
Single supply voltage from 1.8 to 6.0 V
Very low operating current (1.5
μ
A typ.)
Operating temperature from
10 to +70
°
C.
APPLICATIONS
Telemetry data receivers
RF security systems
Low-bit-rate radio data links
Paging applications of UAA2080 and UAA2082 with
software decoding.
GENERAL DESCRIPTION
The OM4031T is intended for performance enhancement
of FSK data receivers that do not have a built-in
post-detection filter.
It contains a digital moving average filter to remove noise
from the demodulated data. When operated from a
38.4 kHz external clock it can handle data rates of 600,
1200 and 2400 bits/s at an oversampling rate of 16. The
filter bandwidth can be doubled to ease the search for bit
synchronization on the output data.
To allow for jitter in the input data, a 12-bit sample is taken
for the majority decision. Doubling the filter bandwidth is
realised by taking the majority out of 6 samples
(2400 bits/s) or by doubling the sampling rate (600 and
1200 bits/s).
An input data rate of 4800 bits/s is supported at 8 times
oversampling and normal bandwidth.
All inputs are Schmitt-triggered to ensure reliable
operation even at signals with long rise/fall times.
QUICK REFERENCE DATA
Notes
1.
2.
V
DD
= 2.0 V; DOUT open-circuit; input data at 20 kHz random pattern.
Bench evaluated for UAA2080H at 470 MHz, not factory tested.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
1.0
1.5
MAX.
UNIT
V
DD
I
DDPD
I
DD
P
i(ref)
supply voltage
power-down supply current
operating supply current
sensitivity improvement at 3% bit error rate note 2
1.8
6.0
10.0
20.0
V
μ
A
μ
A
CE = V
SS
CE = V
DD
; note 1
600 bits/s, 250
μ
s slope
1200 bits/s, 250
μ
s slope
2400 bits/s, 125
μ
s slope
5.3
3.6
2.0
+70
dB
dB
dB
°
C
T
amb
operating ambient temperature
10
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
OM4031T
SO8
plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
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