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參數(shù)資料
| 型號(hào)： | OM4031T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Digital post-detection filter for FSK data receivers |
| 中文描述： | 1-BIT, DSP-DIGITAL FILTER, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, SOT-96-1, SOP-8 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 68K |
| 代理商： | OM4031T |
October 1994
4
Philips Semiconductors
Preliminary specification
Digital post-detection filter
for FSK data receivers
OM4031T
FUNCTIONAL DESCRIPTION
The OM4031T digital post-detection filter oversamples the
noisy binary data stream at input DIN (pin 1), and outputs
a noise-reduced data stream via open-drain output DOUT
(pin 5). The filter bandwidth can be doubled to ease the
search for bit synchronization on the data output signal.
Input sampling takes place at 16 times the data rate. For a
typical clock frequency of 38.4 kHz the nominal data rates
are 600, 1200 and 2400 bits/s. A data rate of 4800 bits/s
can be handled at an oversampling rate of 8 and at normal
bandwidth only.
Using a different clock frequency will produce bit rates
equal to the clock frequency divided by 64, 32 or 16. When
the clock frequency is not an integer multiple of the data
rate some edge jitter will be introduced in the output data.
The clock frequency is not very critical for the noise filtering
performance: a clock frequency of 32.768 kHz could be
used at 512, 1200 and 2400 bits/s without loss of
performance.
Since no on-chip oscillator is available an external clock
signal is required at input CLK (pin 3). Two control inputs
A0 and A1 (pins 6 and 7) are used for selection of the data
rate and the filter bandwidth.
A separate enable input CE (pin 2) allows the circuit to be
powered down. In power-down mode (CE = LOW) the
system clock is inhibited and the data output DOUT is
made 3-state and remains static.
Moving average noise filter
Noise reduction is achieved by applying a moving average
filter on N samples of the input data signal. In principle N
can be odd or even, but in the OM4031T an even number
is used (N = 12). When there is no absolute majority (equal
number of ones and zeroes) the previous majority output
is maintained.
An odd value for N would always produce an absolute
majority and not require decision feedback. However the
noise performance is worse for odd values of N, because
the output can toggle at every clock (e.g. when a 101010...
pattern is clocked in). For even values of N the output
polarity can only change once every 3 clocks and does not
toggle at all for a 101010... or a 11001100... pattern.
Using 12 out of 16 samples for the majority decision
produces a filter which combines good noise reduction
with a large tolerance for data jitter (maximum
1
8
-bit
duration).
Filter implementation
The moving average filter is implemented using a 13-bit
register and two state machines (COUNT and CLOCK) for
the majority decision. The first stage of the shift register is
used for input synchronization.
The CLOCK state machine generates the internal clock
signal CINT and the bandwidth selection signal DBW in
accordance with the logic levels on control lines CE, A0
and A1.
The majority decision is taken by state machine COUNT
based on the contents of the input shift register and the
previous decision in the output latch.
The doubled bandwidth is achieved by increasing the
sampling rate by a factor of 2 for 600 and 1200 bits/s. For
2400 bits/s the number of samples for the majority
decision is halved, controlled by the DBW signal. This
signal is derived from the control signals as follows:
DBW
CE
A0
A1
=
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