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參數(shù)資料
| 型號： | NT7502H-TABF1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65 X 132 RAM-Map LCD Controller / Driver |
| 中文描述： | 65 × 132 RAM的地圖LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 25/54頁 |
| 文件大?。?/td> | 687K |
| 代理商： | NT7502H-TABF1 |
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NT7502
5. Read Status
A0
E
RD
W
R
/
WR
1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
BUSY
ADC
ON/OFF RESET
0
0
0
0
Busy:
When high, the NT7502 is busy due to internal operation or reset. Any command is rejected until BUSY goes low.
The busy check is not required if enough time is provided for each cycle.
Indicates the relationship between RAM column address and segment drivers. When low, the display is reversed
and column address “131-n” corresponds to segment driver n. When high, the display is normal and column
address corresponds to segment driver n.
ON/OFF: Indicates whether the display is on or off. When low, the display turns on. When high, the display turns off. This is
the opposite of Display ON/OFF command
RESET: Indicates the initialization is in progress by RES signal or by reset command. When low, the display is on. When
high, the chip is being reset.
ADC:
6. Write Display Data
Write 8-bit data in display RAM. As the column address automatically increments by 1 after each write, the microprocessor
can continue to write data of multiple words.
A0
E
RD
W
R
/
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
Write data
7. Read Display Data
Reads 8-bit data from display RAM area specified by column address and page address. As the column address
automatically increments by 1 after each write, the microprocessor can continue to read data of multiple words. A single
dummy read is required immediately after column address setup. Refer to the display RAM section of FUNCTIONAL
DESCRIPTION for details. Note that no display data can be read via the serial interface.
A0
RD
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
Read data
8. ADC Select
Changes the relationship between RAM column address and segment driver. The order of segment driver output pads can
be reversed by software. This allows flexible IC layout during LCD module assembly. For details, refer to the column address
section of Figure 4. When display data is written or read, the column address is incremented by 1 as shown in Figure 4.
A0
E
RD
W
R
/
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
0
0
0
D
When D is low, rotation is to the right (normal direction)
When D is high, rotation is to the left (reverse direction)
9. Normal/ Reverse Display
Reverses the Display ON/OFF status without rewriting the contents of the display data RAM.
A0
E
RD
W
R
/
WR
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
0
1
1
D
When D is low, the RAM data is high, with LCD ON potential (normal display)
When D is high, the RAM data is low, with LCD ON potential (reverse display)
25
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