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參數(shù)資料
| 型號： | NT7502H-TABF1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 65 X 132 RAM-Map LCD Controller / Driver |
| 中文描述： | 65 × 132 RAM的地圖LCD控制器/驅(qū)動器 |
| 文件頁數(shù)： | 11/54頁 |
| 文件大?。?/td> | 687K |
| 代理商： | NT7502H-TABF1 |
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NT7502
N
n
n+1
n+2
DATA
BUS holder
MPU
Internal
timing
Incremented
n
n+1
N
N+1
N+2
Preset
N
Set address n
Dummy read
Data Read address n
Data Read address n+1
N
Address preset
Read signal
Column address
R/W
E
A0
Figure. 2
Busy Flag
When the busy flag is “1”, it indicates that the NT7502 chip is running internal processes, and at this time no command aside
from a status read will be received. The busy flag is outputted to D7 pad with the read instruction. If the cycle time (t
CYC)
is
maintained,
it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing
capabilities possible.
Display Data RAM
Display Data RAM
The display data RAM is RAM that stores the dot data for the display. It has a 65 (8 page * 8 bit+1)*132 bit structure. It is
possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure3,
the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at
the time of display common direction, and there are few constraints at the time of display data transfer when multiple NT7502
chips are used, thus display structures with a high degree of freedom can be created easily .
Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an
independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed
asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering).
0
1
0 0 0 0
1 1 1
0 0 0
0
1
D0
D1
D2
D3
D4
COM0
COM1
COM2
COM3
COM4
Display data RAM
Display on LCD
1 1 1
0 0 0
0
0
0
0
0
Figure. 3
11
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