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參數(shù)資料
| 型號： | NT68P62U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 26/56頁 |
| 文件大小： | 528K |
| 代理商： | NT68P62U |
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NT68P62-01
26
13.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 14-bit READ ONLY register, contains information of the Vsync frequency. An internal counter
counts the numbers of 8us pulse between two VSYNC pulses. When a next VSYNC signal is recognized, the counter is
stopped and the VCNTH/L register latches the counter value and then the counter counts from zero again for evaluating next
VSYNC time interval. The counted data can be converted to the time duration between two successive Vsync pulses by time
8 us. If no VSYNC incoming, the counter will overflow and set VCNTOV bit (in VCNTH register) to HIGH. Once the VCNTOV
set to HIGH, it keeps in the HIGH state until writing '1' to it (CLRVOV bit).
Hsync counter: If the ENHSEL bit is set to HIGH, the internal counter counts the Hsync pulses between two Vsync pulses.
The HCNTL/H control registers contain the numbers of Hsync pulse between two Vsync pulses. These data can determine if
the Hsync frequency is valid or not to determine the accurate video mode.
The system supports two other options of interval for user counting the frequency of Hsync pulses. If users clear the
ENHSEL and set the HSEL bits properly, this internal counter counts the Hsync pulses during this system defined time
interval. The time interval is defined below:
ENHSEL
HSEL
Hsync Freq
Note
1
-
Disabled
After system reset or users disabling
0
0
16.384 ms
0
1
32.768 ms
After system reset, this interval will be disabled and the content of ENHSEL & HSEL0 bits are '1'. When this function is
disabled, the HCNTL/H counter is working on the VSYNC pulse. It is invalid to write '00' to them.
Latching the hsync counter: The counted value will be latched by the HCNTH/L register pairs which are updated by Vsync
pulse or system defined time interval. (Refer the Figure 13.4 for the opration of HCNTL/H counter.) If the counter overflows,
the HCNTOV bit (in HCNTH register) will be set to HIGH. Once the HCNTOV is set to HIGH, it keeps in the HIGH state until
writing '1' to it (CLRHOV bit). When setting this CLRHOV bit, the HCNT counter will not be reset to zero.
HSYNCI
VSYNCI
Latch HCNT register
Reset H sync. counter
Start pulse counting
Latch HCNT register
Reset H sync. counter
Start pulse counting
HSYNCI
16.384ms/32.768ms
(Setting HSEL0/1 bits)
Figure 13.4. Hsync Counter Operation
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