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參數(shù)資料
| 型號： | NT68P62U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 19/56頁 |
| 文件大?。?/td> | 528K |
| 代理商： | NT68P62U |
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NT68P62-01
19
Enabling Interrupts: The system will disable all of these
interrupts after reset. Users can enable each of the
interrupts by setting the interrupt enable bits at IENMI,
IEIRQ0 - IEIRQ3 control registers. For example, if users
want to enable external interrupt 0 (INTE0), write '1' to
INTE0 bit in the IENMI control register. At the INTE0 pin,
whenever NT68P62 has detected an interrupt message, it
will generate an interrupt sequence to fetch the NMI vector.
Because these IEX control registers can be read, users can
read back what interrupts he has been activated. At polling
sequence, users need not poll those unactivated interrupts.
Requesting Interrupts to be set: No matter user have been
set the interrupt enable bits or not, if the interrupt triggered
condition is matched, system will set the correspondent bits
in the IRQ0 - IRQ3 control registers or in the NMIPOLL
control register (INTE0 & INTMUTE bits). For example, if at
VSYNCI pin, system have detected a pulse occurring,
system will set the INTV bit in the IRQ2 control register.
Interrupt Groups: System divides IRQ interrupt sources into
several groups, ex IRQ0, IRQ1, IRQ2 and IRQ3. At each of
these groups, if its membership in the one of the interrupt
groups have been activated, its group bit in the IRQPOLL
control register will be set. For example, if the INTS0 of the
first DDC1/2B+ channel is activated, the INTS0 bit in the
IRQ0 will be set and the IRQ0 bit in the IRQPOLL control
register also will be set. Notice that the IRQ0 bit will be
cleared by system when all of its membership of interrupt
sources,
INTS0,
INTTX0,
INTSTOP0 have been cleared by the user or system. The
NMI group is also oprating the same procedure as IRQ
groups.
INTRX0,
INTNAK0
and
Polling Interrupts: When NMI interrupt occurrs, at NMI
interrupt service routine, users must poll the INTE0 &
INTMUTE bit in the NMIPOLL control register to confirm the
NMI interrupt source. The polling sequence decides the
priority of NMI interrupt acceptation. When IRQ interrupt
occurrs, at IRQ interrupt service routine, users must poll the
IRQ0 - IRQ3 in the IRQPOLL control register to confirm the
IRQ interrupt source. In the same way, the polling
sequence decides the priority of IRQ interrupt acception.
When deciding the IRQ source, users can further confirm
the real interrupt source by polling the Correspondent IRQX
control register ($001C - $001E).
Clearing the Interrupt Request bit: When interrupt occurrs,
the CPU will jump to the address defined by the interrupt
vector to execute interrupt service routine. Users can check
which one of the interrupt sources is activated and
operating a tast. It is that upon entering the interrupt service
routine, the request bit that caused the interrupt must be
cleared by user before finishing the service routine and
returning to normal instruction sequence. If users forget to
clear this request bit, after returning to main program, it will
interrupt CPU again because the request bit remains
activated. Simply, users just need write '1' to the polling bits
in the NMIPOLL & IRQX registers ($0016 & $001C -
$001E) to clear those completed interrupt sources.
Selecting interrupt triggered edge: At INTV, INTE0 & INTE1
interrupt sources, these are now edge triggered type.
System provides the selection of rising or falling edge
triggered under users control. After reset, the rising edge
triggered are provided and the content is 'FF' in the
TRIGGER control register ($001F). User just clear control
bits in this TRIGGER register and switch these interrupts to
falling edge triggered.
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