參數(shù)資料
型號(hào)： NT68P62U
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor (32K OTP ROM Type)
中文描述： 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤(pán)形式）
文件頁(yè)數(shù)： 21/56頁(yè)
文件大?。?/td> 528K
代理商： NT68P62U
NT68P62-01
21
12. I/O PORTs
The NT68P62 has 25 pins dedicated to input and output.
These pins are grouped into 4 ports.
12.1. PORT0: P00 - P07
PORT0 is an 8-bit bi-directional CMOS I/O port with PMOS
as internal pull-up (Figure 12.1). Each pin of PORT0 may
be bit programmed as an input or output port without
software control the data direction register. When PORT0
works as output, the data to be output are latched to the
port data register and output to the pin. PORT0 pins that
have '1's written to them are pulled HIGH by the internal
PMOS pull-ups. In this state they can be used as input,
then the input signal can be read. This port output is HIGH
after reset.
P00 - P05 are shared with DAC7 - DAC12 respectively. If
ENDK7 - ENDK12
is set
to LOW in ENDAC register, P00 -
P05 will act as DAC7 - DAC12 respectively (Figure 12.2).
After the chip is reset, ENDK7 - ENDK12 will be in the
HIGH state and P00 - P05s will act as I/O ports.
P06
respectively. If
ENHOUT
HVCON register, P06
HSYNCO respectively (Figure 12.3). After the chip is reset,
ENHOUT
&
ENVOUT
will be in the HIGH state and
P06
P07 will act as I/O pins.
P07 are shared with VSYNCO & HSYNCO
ENVOUT
is set
to LOW in
P07 will act as VSYNCO &
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0000
$0007
PT0
FFH
FFH
P07
P06
P05
P04
P03
HPOLI
P02
VPOLI
P01
HPOLO
P00
VPOLO
RW
R
-
-
HSYNCI
VSYNCI
HV CON
FFH
ENHOUT
ENVOUT
-
-
-
-
HPOLO
VPOLO
W
$000F
ENDAC
FFH
-
-
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
ENDK7
W
V
DD
I/O
Data Out
Data In
Figure 12.1. I/O Structure
PWM
Output
PWM
Data In
Figure 12.2. PWM Output Structure
V
DD
O/P
Data Out
Figure 12.3. Output Structure
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