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參數(shù)資料
| 型號(hào)： | NT68P62U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 528K |
| 代理商： | NT68P62U |
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NT68P62-01
13
6. Timing Generator
This block generates the system timing and control signal
to be supplied to the CPU and on-chip peripherals. A
crystal quartz, ceramic resonator, or an external clock
signal which will be provided to the OSCI pin generates
system timing. It generates 8MHz system clock, 4MHz for
the CPU. Although internal circuits have a feedback resister
and compacitor included, users can externally add these
components for proper operating.
The typical clock frequency is 8MHz. Different frequencies
will affect the operation of those on-chip peripherals whose
operating frequency is based on the system clock.
8MHz
OSCI
OSCO
NT68P62
OSCI
NT68P62
Figure 6.1. Oscillator Connections
(1)
(2)
Unconnected
External Clock
OSCO
7. RESET
The NT68P62 can be reset by the external reset pin or by
the internal watch-dog timer. This is used to reset or start
the microcontroller from a POWER DOWN condition.
During the time that this reset pin is held LOW (*reset line
must be held LOW for at least two CPU clock cycles),
writing to or from the
μ
C is inhibited. When a positive edge
is detected on the RESET input, the
μ
C will immediately
begin the reset sequence.
After a system initialization time of six CPU clock cycles,
the mask interrupt flag will be set and the
μ
C will load the
program counter from the memory vector locations $FFFC
and $FFFD. This is the start location for program control.
An internal Schmitt Trigger buffer at the RESET pin is
provided to improve noise immunity.
The reset status is as follows:
1. PORT0
will act as I/O ports with HIGH output
2. Sync processor counters reset and VCNT | HCNT
latches cleared
3. All sync outputs are disabled
4. Base timer is disabled and cleared
5. Various Interrupt sources are disabled and cleared
6. A/D converter is disabled and stopped
7. DDC1/2B+ function is disabled
8. PWM DAC0 – DAC6 output 50% duty waveform and
DAC7 - DAC12 is disabled
9. Watch-dog timer is cleared and enabled
PORT1
PORT2
PORT3 (& PORT4) pins
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