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參數(shù)資料
| 型號(hào)： | NT68P62-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 36/56頁 |
| 文件大小： | 528K |
| 代理商： | NT68P62-01 |
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NT68P62-01
36
(iSecond Byte Data
to CH0TXDAT register
User can load next byte data
register to shift register
Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface
The built-in DDC2B+ I
2
C bus Interface features as follows
-
SLAVE mode (NT68P62 is addressed by a master
which drives SCL signal)
-
MASTER mode (NT68P62 addresses external device
and send out SCL clock)
-
Compatible with I
2
C bus standard
-
One default address (A0H) and one programable
address
-
Automatic wait state insertion
-
Interrupt generation for status control
-
Detection of START and STOP signals
The DDC2B+ will be activated as SLAVE mode initially.
Users can switch to MASTER mode by clearing the
bit under either of these conditions listed as follows:
1. After entering to DDC1 function and clearing this bit, the
system will be changed from DDC1 to DDC2B+
MASTER mode operation.
2. After entering to DDC2B+ slave mode function and
clearing this bit, the system will changed from slave
mode into master mode operation.
As clearing
condition and wait for user to put the calling address into
CH0/1TXDAT control register. Notice that user must
predetermine the direction of master mode transmission
before putting calling address.
Below is the DDC2B+ function with channel 0, and the
manipulation of channel 1 is the same as channel 0.
bit, system will send out a 'START'
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