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參數(shù)資料
| 型號： | NT68P62-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 18/56頁 |
| 文件大小： | 528K |
| 代理商： | NT68P62-01 |
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NT68P62-01
18
DDC Channel 0/1 Maskable Interrupt Sources:
Interrupt
Meaning
Action
INTS INT
SCL Go-Low INT
In DDC1 mode, it will be activated when the external device proceed a DDC2
communication. This action includes pull the SCL line to ground or send out an
'START' condition directly. System will respond to this action by changing
DDC1 mode to DDC2 slave mode.
INTA INT
Address Matched
INT
It will be activated at DDC2 slave mode when the external device call NT68P62
slave address. If this calling address matches the NT68P62 address, system
will generate this interrupt to remind user
INTTX INT
Transfer Buffer
Empty INT
It will be activated at DDC2 mode when transmission buffer, IIC_TXDAT, is
empty at transmission mode.
INTRX INT
Receiving Buffer
Overflow INT
It will be activated at DDC2 mode when new data have store in the
IIC_RXDAT register at receive mode.
INTNAK INT
No Acknowledge
INT
At transmission mode, this interrupt will be activated when NT68P62 have
send out one byte data but the external device does not respond an
acknowledge bit to it.
INTSTOP INT
DDC2 Stop INT
In SLAVE mode, this interrupt will be activated when the NT68P62 receives an
'STOP' condition.
INTSTOP0
INTNAK0
INTRX0
INTTX0
INTA0
INTS0
INTSTOP1
INTNAK1
INTRX1
INTTX1
INTA1
INTS1
INTMR
INTE1
INTV
INTADC
INTMUTE
INTE0
IRQ0
IRQ (to CPU 6502)
NMI (to CPU 6502)
IRQ0
IRQ1
IRQ2
Figure 11.1. Interrupt Controller Structure
IRQ1
IRQ2
IEIRQ0
IEIRQ1
IEIRQ2
NMIPOLL
IENMI
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