- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363670 > NT68P62-01 (Electronic Theatre Controls, Inc.) 8-Bit Microcontroller for Monitor (32K OTP ROM Type) PDF資料下載
參數(shù)資料
| 型號(hào)： | NT68P62-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| 中文描述： | 8位微控制器的監(jiān)視器（32K的檢察官辦公室光盤形式） |
| 文件頁數(shù)： | 34/56頁 |
| 文件大?。?/td> | 528K |
| 代理商： | NT68P62-01 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
NT68P62-01
34
15. I
2
C Bus Interface: DDC1 & DDC2B Slave Mode
Interface: I
2
C bus interface is a two-wire, bi-directional
serial bus which provides a simple, efficient way for data
communication between devices, and minimizes the cost of
connecting among various peripheral devices. NT68P62
provides two I
2
C channels. Both of them are shared with
I/O pins and their structures are open drain. When the
system is reset, these channels are originally general I/O
pins structure. All of these I
2
C bus function will be activated
only after their ENDDC bits are cleared to '0' (CH0/1CON
registers).
DDC1 & DDC2B+ function: Two modes of operation have
been implemented in NT68P62, uni-directional mode
(DDC1 mode) and bi-directional mode (DDC2B+ mode).
These channels will be activated as DDC1 function initially
when users enable DDC function. These channels will
switch automatically to DDC2B+ function from DDC1
function when a low pulse greater than 500ns is detected
on the SCL line. Users can start a master communication
directly from DDC1 communication by clearing MODE bit
in the CH0/1CLK control register.
The channels can return to DDC1 function when users set
the MD1/2 bit to '1' in the CH0/1CON registers.
15.1. DDC1 bus interface
Vsync input and SDA pin: In DDC1 function, the Vsync pin
is used as input clock pin and SDA pin is used as data
output pin. This function comprises two data buffers: one is
preloading data buffer for putting one byte data in advance
by user (CH0/1TXDAT), and the other is shift register for
shifting out one bit data to SDA line, which users can not
access directly. These two data buffer cooperate properly.
For the timing diagram please refer to Figure 15.1. After
system resets, the I
2
C bus interface is in DDC1 mode.
Data transfer: At first, user must put one byte transmitted
data into CH0/1TXDAT register in advance, and activate
I
2
C bus by setting ENDDC bit to '0'. Then open INTTX0/1
interrupt source by setting INTTX0/1 to '1' in the IEIRQ0/1
registers. On the first 9 rising edges of Vsync, system will
shift out invalid bit in shift register to SDA pin to empty shift
register. When shift register is empty and on next rising
edge of Vsync, it will load data in the CH0/1TXDAT
registers to internal shift register. At the same time,
NT68P62 will shift out MSB bit and generate an INTTX0/1
interrupts to remind user to put next byte data into
CH0/1TXDAT register. After eight rising clocks, there have
been eight bits shifted out in proper order and shift register
becomes empty again. At the ninth rising clock, it will shift
the ninth bit (null bit '1') out to SDA. And on the next rising
edge of Vsync clock, system will generate an INTTX0/1
interrupts again. By the same way, NT68P62 will load new
data from CH0/1TXDAT registers to internal shift register
and shift out one bit right away. Beware that user should
put one new data into CH0/1TXDAT registers properly
before the shift register is empty (the next INTTX0/1
interrupt). If not, the hardware will tansmit the last byte data
repeatedly.
Vsync clock: Only in the separate SYNC mode, can the
Vsync pulse be used as data transfer clock, its frequency
can be up to 25KHz maximum. In composite Vsync mode,
NT68P62 can not transmit any data to SDA pin, regardless
whether the Vsync can be extracted from composite Hsync
signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT68P62U | 8-Bit Microcontroller for Monitor (32K OTP ROM Type) |
| NT7181 | LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface |
| NT7181F | LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface |
| NT7181FQ | LVDS Transmitter 24 Bit Color Host-LCD Display Panel Interface |
| NT7501 | 33 X 100 RAM-Map LCD Controller/Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT6C34CA | 制造商:ASTEC 功能描述: 制造商:Emerson Network Power - Embedded Power 功能描述: |
| NT6DM32M16AD-T1 | 制造商:Nanya Technology Corporation 功能描述:MOBILE DRAM |
| NT6DM32M16BD-T1 | 制造商:NANYA TECHNOLOGY 功能描述:512M LPDDR SDRAM, 32Mx16, 200MHz 制造商:NANYA TECHNOLOGY 功能描述:NT6DM32 Series 1.8 V 512 Mb (32 Mb x 16) 200 MHz SDRAM - FBGA-60 |
| NT6DM64M16BD-T1 | 制造商:Nanya Technology Corporation 功能描述:MEMORY IC |
| NT6DM8M32AC-T3 | 制造商:NANYA TECHNOLOGY 功能描述:NT6DM8M32 Series 1.8 V 256 Mb (8 M x 32) 166 Mhz SDRAM - BGA-90 制造商:NANYA TECHNOLOGY 功能描述:NT6DM8M32AC Series 256-Mbit (8 M x 32) 166 Mhz LPDDR SDRAM - BGA-90 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。