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參數(shù)資料
| 型號： | NT6861U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor |
| 中文描述： | 8位微控制器的監(jiān)控 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大小： | 455K |
| 代理商： | NT6861U |
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NT6861
34
STOP condition: When SCL & SDA lines have been
released (remain in 'HIGH' state), DDC2B data transfer is
always terminated by a STOP condition generated by
external device. A STOP signal is defined as a low to high
transition of SDA while SCL is in HIGH state. When there is
a STOP condition, NT6861 will set the 'STOP' bit to '1' and
user can poll this status bit to control DDC2B transmission
at any time. This bit keeps '1' until user clears it. Notice the
SCL and SDA lines must conform to I
2
C bus specifications.
(Refer to Figure 26). Refer to the standard I
2
C bus
specification for details.
Changing to DDC1 mode: After an external device
terminates DDC2 transmission, set MDI/ 2
to 1 for
changing to DCC1 mode. When the SCL line has been
released (pulled-up), user can force NT6861 to DDC1
mode communication at any time. This function is
supporting the 'error' recovery protocol in the VESA DDC
standard Ver 2.0.
Control bit description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0005
MD CON
07H
-
-
-
-
-
-
-
-
-
INSEN
-
HSEL
S/ C
S/ C
MD1/
2
MD1/
2
R
W
$000F
IEX
00H
-
-
IEINTS
IEINTD
IEINTA
IEINTR
IEINTE
IEINTV
W
$0010
IRQX
00H
-
-
IRQINTS
IRQINTD
IRQINTA
IRQINTR
IRQINTE
IRQINTV
R
$0011
CLR FLG
00H
CLRHOV
CLRVOV
CLRINTS
CLRINTD
CLRINTA
CLRINTR
CLRINTE
CLRINTV
W
$0013
II ADR
FFH
AR7
AR6
AR5
AR4
AR3
AR2
AR1
-
W
$0014
II DAT
00H
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RW
$0015
II STS
08H
-
-
START
START
STOP
STOP
ENDDC
TRX
RXAK
-
R
W
MDCON control register:
MD1/2 : Select the DDC mode - '1' for DDC1 and '0' for
DDC2B mode. System will be DDC1 mode by
default.
When transmission mode is changed form
DDC1 to DDC2B, system will automatically clear
this bit.
IEX control register:
In DDC2 mode, user use INTS, INTA & INTD interrupt and
II_STS control register to control DDC2B transmission.
II_DAT control register: Data buffer for transmission
II_ADR control register: User can define the address of
DDC2B device. If an external
device sends the same address
data as this control register
(calling
will generate an INTA interrupt.
NT6861),
NT6861
II_STS control register:
ENDDC: When clearing this bit, the system will activate
DDC transmission. P30 and P31 will switch to
SDA and SCL pin.
TRX: In the READ mode of DDC2B transmission, user
must set this bit '1'.
RXAK: In the WRITE mode of DDC2B transmission, after
one byte has been sent out to the SDA line,
there will be an INTD interrupt. At INTD interrupt
service routine, user can check this bit to see if
external device has responded to NT6861.
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