參數(shù)資料
型號(hào): NT6861U
廠商: Electronic Theatre Controls, Inc.
英文描述: 8-Bit Microcontroller for Monitor
中文描述: 8位微控制器的監(jiān)控
文件頁數(shù): 32/44頁
文件大小: 455K
代理商: NT6861U
NT6861
32
14.2
DDC2B Slave Mode bus interface
The DDC2B I
2
C Bus Interface features are as follows:
- SLAVE mode (NT6861 addressed by a master
which drive SCL signal)
- Fully compatible with I
2
C bus standard
- Interrupt and generation of acknowledge handled by
user for communication
- Interrupt driven byte by byte data transfer
- Calling address identification interrupt
- Detection of START and STOP signals
Enable I
2
C and INTS: The NT6861 included the use in
applications requiring storage and serial transmission of
configuration and control information. User can place
address data into IIADR register and set IEINTS to '1' (in
IEX register) in advance. In the DDC1 mode (after clearing
ENDDC
to '0') and when the low level on the SCL pin
occurs, NT6861 will remind user by generating a INTS
interrupt and switch to DDC2B mode automatically. When
user sets MD1/2
to '1' at this time, the NT6861 will still
proceed with a DDC1 communication. The DDC2B bus
consists of two wires, SCL and SDA; SCL is for the data
transmission clock and SDA is for the data line. Data
transfers follow the format shown in Figure 19. The
standard communication of I
2
C bus protocol includes four
parts: a START signal, slave ADDRESS, transferred data
(proceed byte by byte) and a STOP signal. In the wired-
AND connection, any slow devices can hold the SCL line
LOW to force the fast device into a wait state until the slow
device is ready for the next bit or byte transfer in a type of
handshake procedure.
8
7
6
5
1
8
7
ACK
5
4
3
1
8
6
2
7
1 - 7
SCL
8
9
1 - 7
8
9
1 - 7
8
9
SDA
START
CONDITION
STOP
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
4
IIDAT Reg.
bit stream
MSB
MSB
MSB
LSB
LSB
ACK
Figure 23. DDC2B Data Transfer
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