參數(shù)資料
型號(hào)： NT6861U
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor
中文描述： 8位微控制器的監(jiān)控
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 455K
代理商： NT6861U
NT6861
15
8. RESET
NT6861 can be reset by the external reset pin or by the
internal watch-dog timer. This resets or starts the
microcontroller from a power-down condition. During the
time that this reset pin is held low (*reset line must be held
low for at least two CPU clock cycles), writing to or from the
μ
C is inhibited. When positive edge is detected on the
reset input, the
μ
C will immediately begin reset sequence.
After a system initialization time of six CPU clock cycles,
the mask interrupt flag will be set and the
μ
C will load the
program counter from the memory vector locations $FFFC
and $FFFD. This is the start location for program control.
To improve noise immunity a Schmitt Trigger buffer is
provided at the RESET
.
Reset status is as follows:
1. PORT0 PORT1. PORT2. PORT3 pins will act as
I/O ports with HIGH output.
2. Sync processor counters reset and VCNT | HCNT
latches cleared
3. All sync outputs are disabled
4. Base timer is disabled and cleared
5. A/D Converter is disabled and stopped
6. DDC1/2B function is disabled
7. PWM DAC0 - DAC7 output 50% duty
waveform and DAC8 - DAC13 is disabled
8. Watch-dog timer is cleared and enabled
This RESET
pin must be pulled high by external pulled-up
resistor (5K
suggestion), or it will stay low voltage to reset
system all the time (Refer to Figure 5 ).
9.
Watch-dog timer (WDT)
NT6861 implements a watch-dog timer reset to avoid
system shut-down or malfunction. The clock of the WDT is
from on-chip RC oscillator not requiring any external
components. The WDT runs regardless if the clock of the
OSCI/OSCO pins of the device has been stopped. The
WDT time interval is about 0.5 second. The WDT must be
cleared within every 0.5 second when software is in normal
sequence, otherwise the WDT will overflow and cause
reset. The WDT is cleared and enabled after system is
reset. It cannot be disabled by software. Users can clear
the WDT by writing 55H to CLRWDT register.
as;
LDA
STA
#$55
$0012
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0012
CLR WDT
-
0
1
0
1
0
1
0
1
W
N
Reset_
5
O
Vcc
External
Low Voltage
Reset Circuit
Figure 5. External Reset Suggested Circuit
相關(guān)PDF資料
PDF描述
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