- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363670 > NT6861U (Electronic Theatre Controls, Inc.) 8-Bit Microcontroller for Monitor PDF資料下載
參數(shù)資料
| 型號： | NT6861U |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor |
| 中文描述： | 8位微控制器的監(jiān)控 |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 455K |
| 代理商： | NT6861U |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
NT6861
23
12.2. Sync Processor Control Register:
Composite sync: User has to determine whether the
incoming signal is separate sync or composite sync and
set S/C
& HSEL bit properly. If composite sync signal is
input, after set S/C
to '0', the sync separator block will be
activated ( please refer figure 18). During Vsync pulse the
Hsync will be inserted Hsync pulse by hardware circuit and
the pulse width of inserted pulse is 2
μ
s fixed. According to
the last Hsync pulse outside the Vsync pulse duration, the
hardware will arrange the interval of these hardware
interpolated pulse. So the insertion of these Hsync pulse
will be continued inside the Vsync pulse duration no matter
what the Hsync pulse originally exist or not. These inserted
Hsync pulse have 0.5
μ
s phase deviation maximum. The
Vsync pulse can be extracted by hardware from composite
signal, and the output of Vsync signal delay time will be
limited bellow 20ns. For inserting Hsync pulse safely, the
extracted Vsync pulse will be widen about 9
μ
s. Because
evenly putting the Hsync pulse, the last inserted Hsync
pulse will have different frequency from original ones.
System will not implement this insertion function, user
must clear INSEN
bit in the MD_CON control register to
activate this function.
After reset, the HSEL, S/ C
& INSEN
bits default value is
HIGH and clear the VCNT | HCNT counter latches to zero.
Polarity: The detection of Hsync or Vsync polarity is
achieved by hardware circuits sample the sync signal's
voltage level periodically. The user can read HPOLI &
VPOLI bit in HVCON register, from which bit = '1'
representing positive polarity and '0', negative polarity. The
user can read HSYNCI and VSYNCI bit in HVCON register
to detect H & V sync input signal. The user can control the
polarity of H & V sync output signal by writing the
appropriate data to the HPOLO and VPOLO bits in the
HVCON register, '1' represents positive polarity and '0',
negative polarity.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output which are shared with
P06 & P07 respectively. If set ENV
& ENH
to '0' in
SYNCON register, P06 & P07 will act as VSYNCO &
HSYNCO pin. When input sync is separate signal, the
V/HSYNCO will output the same signal as input sync
signal without delay. But if input sync is composite signal,
the VSYNCO signal will have a delay time of about 4
μ
s to
8
μ
s. The HSYNCO has no delay output and still has Vsync
pulse among Hsync pulse (i.e. the signal on HSYNCI pin
directly output to HSYNCO pin.)
Free run signal output: The user can set FRUN
to '0' bit in
SYNCON register, then VSYNCO will output 61Hz Vsync
signal and HSYNCO will output 62.5KHz Hsync signal
default (Refer to Figure 20). When FRFREQ
bit clears to
'0', the HSYNCO pin will output 41.7 KHz Hsync signal.
The free run signal has negative or positive polarity
depending on the HPOLO & VPOLO bit setting in the
HV_CON control register, '1' is positive and '0' is negative
polarity. After chip reset, ENV
,
ENH
,
FRFREQ
& FRUN
will enter HIGH state and P06 & P07 will act as I/O pins.
Half frequency input and output: In this pin assignment,
when ENHALF
sets to
'0' in SYNCON register, the
HALFHO pin will act as an output pin and output half of
input signal in the HALFHI pin with 50% duty
(Refer to Figure 21). If NOHALF
sets
to '0', HALFHO will
output the same signal in the HALFHI pin and user can
control its polarity output of HALFHO by setting HALFPOL
bit, '1' for positive and '0' for negative polarity. After chip
reset, ENHALF
,
NOHALF
& HALFPOL will be in the
HIGH state and P13 & P17 will act as I/O pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT6861 | 8-Bit Microcontroller for Monitor |
| NT6862 | 8-Bit Microcontroller for Monitor |
| NT6862U | 8-Bit Microcontroller for Monitor |
| NT6868A | Keyboard Controller |
| NT6868A-0011 | Keyboard Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT6862 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor |
| NT68625 | 制造商:NAIS 制造商全稱:Nais(Matsushita Electric Works) 功能描述: |
| NT6862U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor |
| NT68667 | 制造商:NAIS 制造商全稱:Nais(Matsushita Electric Works) 功能描述:NOVATEK顯示器驅(qū)動芯片 |
| NT6868A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Keyboard Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。