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參數(shù)資料
| 型號： | NT511740C5J-60 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTC?s CMOS silicon gate technology. |
| 中文描述： | 該NT511740C5J是4194304字× 4位動(dòng)態(tài)隨機(jī)存儲(chǔ)器的NTC熱敏假的嗎？擰CMOS硅柵技術(shù)。 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 336K |
| 代理商： | NT511740C5J-60 |
11
NANYA TECHNOLOGY CORP
NANYA TECHNOLOGY CORP.
reserves the right to change products and specifications without notice.
NT5117405J
4,194,304-word X 4-bit
Dynamic RAM : Fast Page Mode with EDO
1.
A start-up delay of 200
μ
s is required after po/WEr-up,follo/WEd by a minimum of eight
initialization cycles (/RAS-only refresh or /CAS before /RAS refresh) before proper device operation
is achieved.
2.
The AC characteristics assume t
T
=2 ns.
3.
V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals. Transition time (t
T
)
are measured bet/WEen V
IH
and V
IL
.
4.
This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5.
Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only . If t
RCD
is greater than the specified
t
RCD
(Max.) limit, access time is controlled by t
CAC
.
6. Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only . If t
RAD
is greater than the specified
t
RAD
(Max.) limit, access time is controlled by t
AA
.
7.
t
CEZ
(Max.), t
REZ
(Max.), t
/WEZ
(Max.) and t
/OEZ
(Max.) define the time at which the output achieves the
open circuit condition and are not referenced to output voltage levels.
8.
t
CEZ
and t
REZ
must be satisfied for open circuit condition .
9.
t
RCH
or t
RRH
must be satisfied for a read cycle.
10.
t
WCS
, t
CWD
, t
RWD
, t
AWD
, and t
CPWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only . If t
WCS
ù
(Min.), the cycle is an early write cycle and the
data out will remain open circuit (high impedance) throughout the entire cycle. If t
CWD
ù
t
RWD
ù
(Min.) , t
AWD
ù
(Min.) and t
CPWD
ù
(Min.), the cycle is a read modify write cycle
and data out will contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.
11.
These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading
edge in an /OE control write cycle or a read modify write cycle .
12.
The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not
used and each DQ pin now accesses 8-bit locations .Since all 4 DQ pins are used, a total of 32
data bits can be written in parallel into the memory array. In a read cycle, if 8 data bits are equal the
DQ pin will indicate a high level. If the 8 data bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by performing
a /RAS-only refresh cycle or a /CAS before /RAS refresh cycle.
13.
In a test mode read cycle , the value of access time parameters is delayed for 5 ns for the specified
value . These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
(Min.) ,
Notes:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT511740C5J-70 | The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTC?s CMOS silicon gate technology. |
| NT511740D0J-60 | The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
| NT511740D0J-6L | The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
| NT511740D0J | The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
| NT511740D0J-50 | The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT511740C5J-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTC?s CMOS silicon gate technology. |
| NT511740D0J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
| NT511740D0J-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
| NT511740D0J-5L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
| NT511740D0J-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The NT511740C5J is a 4,194,304-word x 4-bit dynamic RAM fabricated in NTCs CMOS silicon gate technology. |
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