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參數(shù)資料
| 型號(hào)： | NSC800E |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| 中文描述： | NSC800TM高性能低功耗CMOS微處理器 |
| 文件頁數(shù)： | 12/76頁 |
| 文件大?。?/td> | 785K |
| 代理商： | NSC800E |
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8.0 Functional Description
(Continued)
8.3 CPU WORKING AND ALTERNATE REGISTER SETS
8.3.1 CPU Working Registers
The portion of the register array shown in Figure 4b repre-
sents the CPU working registers. These sixteen 8-bit regis-
ters are general-purpose registers because they perform a
multitude of functions, depending on the instruction being
executed. They are grouped together also due to the types
of instructions that use them, particularly alternate set oper-
ations.
The F (flag) register is a special-purpose register because
its contents are more a result of machine status rather than
program data. The F register is included because of its inter-
action with the A register, and its manipulations in the alter-
nate register set operations.
8.3.2 Alternate Registers
The NSC800 registers designated as CPU working registers
have one common feature: the existence of a duplicate reg-
ister in an alternate register set. This architectural concept
simplifies programming during operations such as interrupt
response, when the machine status represented by the con-
tents of the registers must be saved.
The alternate register concept makes one set of registers
available to the programmer at any given time. Two instruc-
tions (EX AF, A‘F’ and EXX), exchange the current working
set of registers with their alternate set. One exchange be-
tween the A and F registers and their respective duplicates
(A’ and F’) saves the primary status information contained in
the accumulator and the flag register. The second exchange
instruction performs the exchange between the remaining
registers, B, C, D, E, H, and L, and their respective alter-
nates B’, C’, D’, E’, H’, and L’. This essentially saves the
contents of the original complement of registers while pro-
viding the programmer with a usable alternate set.
CPU Main Working Register Set
Accumulator A
Register B
Register D
Register H
(8)
(8)
(8)
(8)
Flags F
Register C
Register E
Register L
(8)
(8)
(8)
(8)
CPU Alternate Working Register Set
Accumulator A’
Register B’
Register D’
Register H’
(8)
(8)
(8)
(8)
Flags F’
Register C’
Register E’
Register L’
(8)
(8)
(8)
(8)
FIGURE 4b. CPU Working and Alternate Registers
8.4 REGISTER FUNCTIONS
8.4.1 Accumulator (A Register)
The A register serves as a source or destination register for
data manipulation instructions. In addition, it serves as the
accumulator for the results of 8-bit arithmetic and logic op-
erations.
The A register also has a special status in some types of
operations; that is, certain addressing modes are reserved
for the A register only, although the function is available for
all the other registers. For example, any register can be
loaded by immediate, register indirect, or indexed address-
ing modes. The A register, however, can also be loaded via
an additional register indirect addressing.
Another special feature of the A register is that it produces
more efficient memory coding than equivalent instruction
functions directed to other registers. Any register can be
rotated; however, while it requires a two-byte instruction to
normally rotate any register, a single-byte instruction is
available for rotating the contents of the accumulator (A reg-
ister).
8.4.2 F Register - Flags
The NSC800 flag register consists of six status bits that
contain information regarding the results of previous CPU
operations. The register can be read by pushing the con-
tents onto the stack and then reading it, however, it cannot
be written to. It is classified as a register because of its
affiliation with the accumulator and the existence of a dupli-
cate register for use in exchange instructions with the accu-
mulator.
Of the six flags shown in Figure 5, only four can be directly
tested by the programmer via conditional jump, call, and
return instructions. They are the Sign (S), Zero (Z), Parity/
Overflow (P/V), and Carry (C) flags. The Half Carry (H) and
Add/Subtract (N) flags are used for internal operations re-
lated to BCD arithmetic.
TL/C/5171–23
FIGURE 5. Flag Register
12
相關(guān)PDF資料 |
PDF描述 |
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| NSC800N | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC800V | NSC800TM High-Performance Low-Power CMOS Microprocessor |
| NSC858 | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858D | NSC858 Universal Asynchronous Receiver/Transmitter |
| NSC858E | NSC858 Universal Asynchronous Receiver/Transmitter |
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| NSC800E-1/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800E-1M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800E-3/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800E-3M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
| NSC800E-4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microprocessor |
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