參數(shù)資料
型號(hào): NSC800E
廠商: National Semiconductor Corporation
英文描述: NSC800TM High-Performance Low-Power CMOS Microprocessor
中文描述: NSC800TM高性能低功耗CMOS微處理器
文件頁(yè)數(shù): 10/76頁(yè)
文件大小: 785K
代理商: NSC800E
8.0 Functional Description
This section reviews the CPU architecture shown below, fo-
cusing on the functional aspects from a hardware perspec-
tive, including timing details.
As illustrated in Figure 1, the NSC800 is an 8-bit parallel
device. The major functional blocks are: the ALU, register
array, interrupt control, timing and control logic. These areas
are connected via the 8-bit internal data bus. Detailed de-
scriptions of these blocks ae provided in the following sec-
tions.
TL/C/5171–9
Note:
Applicable pinout for 40-pin
dual-in-line package within parentheses
FIGURE 1. NSC800 CPU Functional Block Diagram
10
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