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參數(shù)資料
| 型號(hào)： | NSBMC096 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Memory Controller(脈沖存儲(chǔ)控制器) |
| 中文描述： | 突發(fā)內(nèi)存控制器（脈沖存儲(chǔ)控制器） |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | NSBMC096 |
Functional Description
(Continued)
The bus monitor operates by monitoring the state of the
DEN signal. Should it be asserted for longer than the pro-
grammed
Bus Time Out
value in configuration register 7,
Ready
is asserted if configuration bit 63 is set. If configura-
tion bit 62 is set, BERR is also asserted. The BERR signal
behaves much like the timer interrupt in that it can be pro-
grammed to produce a pulse or a level state.
If level state operation is selected, (configuration bit 61
e
1), BERR will only be deasserted when configuration regis-
ter 7 is accessed in a read cycle. If configuration bit 61 is
cleared to zero, a two cycle pulse is produced on time-out.
By providing both modes of operation, the BERR signal may
be connected directly to the processor, or to an external
WATCHDOG
TM
circuit.
OPERATION CONTROL FIELD
Byte 0 of the configuration register contains three fields.
The first field (from LSB) is reserved for test purposes and
must be zero for proper in-circuit operation. The second
field is the operation control field which is used to control
the state of the page cache, timer, interrupts and bus error
signal. The third field is the Iow two bits of the refresh rate.
The NSBMC096 has been designed such that if any of the
bits in the operation control field is written with a ‘‘1’’, ac-
cess to the other two fields is disabled and the previous
value is retained. If all bits in the operation control field are
‘‘0’’, the reserved and refresh rate fields are updated from
the current input.
Since the control register is accessed as a byte, automatic
masking of the non-control field bits simplifies programming
of the control parameters. AII parameters in this field may
be modified on-the-fly, and all functions are disabled by re-
set. The operational controls have been encoded such that
any access to the register will only modify one parameter.
Bit
Control
Function
7
6
5
4
3
2
1
0
D
X
D
X
0
0
0
1
0
0
0
0
D
X
D
X
Update Bits 0, 1, 6 and 7 with data D
Instruction Access Page Cache Disable
(Default)
Instruction Access Page Cache Enable
Data Access Page Cache Disable (Default)
Data Access Page Cache Enable
Acknowledge Timer Interrupt
Enable Timer Output for Level Sense
Interrupt
Disable All Timer Interrupts
Enable Timer Output for Edge Sense
Interrupt
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
0
1
0
0
X
X
X
X
PAGE CACHE MANAGEMENT
The
NSBMC096 incorporates a mechanism whereby advantage
can be taken of the page access mode of DRAMs, not only
for burst access, but also for non-sequential data and in-
struction access. The mechanism relies on the fact that as
long as RAS is asserted, access to the selected row can be
gained by simply asserting a column address and the CAS
strobe. The resulting access is slower than a burst only by
the amount of time required to ensure that the desired ad-
dress is in the same row as was previously selected.
Page
Cache
management
implemented
by
the
The benefits of this type of access are obvious, however,
there can be drawbacks. If the required address does not
reside in the same page as that selected, the currently se-
lected row must be released and the new row selected be-
fore the access can proceed. The process of de-selecting a
row and selecting a new one requires that the RAS pre-
charge time be allowed to expire before the selection of a
new row can begin. This pre-charge time can require up to
two additional cycles over a standard access startup.
The efficiency of this type of cache (PCache) is related to a
large extent on the locality of reference of the datum being
accessed. For systems that have mixed Instruction and
Data memory systems, PCache efficiency is very dependent
on the behavior of the program being executed as related to
the ‘‘run-length’’ of data and instruction access, the proces-
sor internal cache utilization, and the locality of data and
instruction references. Since throughput is lowered by
cache misses, the page cache can be dynamically enabled/
disabled for instruction and/or data access. In this manner
the programmer can apply the mechanism judiciously in or-
der to maximize throughput.
For systems in which Instruction and data spaces are con-
trolled by independent NSBMC096s, the page cache man-
agement can be used to greater effect as data and instruc-
tion ‘‘run length’’ ceases to be a factor in determining per-
formance. In this type of configuration cache efficiency is
simply a function of locality of reference and a control strat-
egy for the page cache mechanism is much simpler to de-
rive and implement. PCache management is independently
controlled for instruction and data access. A recommended
starting strategy for improving performance of mixed in-
struction/data systems is to rely on the burst mechanism
and the internal cache for instruction fetching, and enable
PCache for Data access only. This general rule of thumb
can be improved on, once program behavior is bench-
marked.
9
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| NSBMC033 | Burst Memory Controller(脈沖存儲(chǔ)控制器) |
| NSBMC096VF | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096-16 | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC290-16 | Burst Mode Memory Controller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC096-16 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
| NSBMC096VF-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
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