參數(shù)資料
型號: NSBMC096
廠商: National Semiconductor Corporation
英文描述: Burst Memory Controller(脈沖存儲控制器)
中文描述: 突發(fā)內(nèi)存控制器(脈沖存儲控制器)
文件頁數(shù): 13/18頁
文件大?。?/td> 266K
代理商: NSBMC096
Timing Parameters
(Continued)
TL/V/11805–11
FIGURE 8. Burst Access w/t PCache Hit
Figures 8 and 9 show the sequence of events that can oc-
cur when PCache is enabled. The sequence in Figure 8
shows two back-to-back bursts in the same page. This type
of sequence yields the highest data transfer rate achievable
with DRAM. Figure 9 shows the worst case scenario. This
example shows two back-to-back simple access to different
rows with PCache is enabled.
TL/V/11805–12
FIGURE 9. Simple Access w/t PCache Miss
13
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