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參數(shù)資料
| 型號(hào)： | NSBMC025 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Memory Controller(脈沖存儲(chǔ)控制器) |
| 中文描述： | 突發(fā)內(nèi)存控制器（脈沖存儲(chǔ)控制器） |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 266K |
| 代理商： | NSBMC025 |
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AC Timing Parameters
(Unless otherwise stated V
CC
e
5.0V
g
5%, 0
§
C
k
T
A
k
70
§
C.)
Symbol
Description
16 MHz
25 MHz
33 MHz
Units
Min
Max
Min
Max
Min
Max
1.
t
ADSU
Address Strobe Setup Time
14
12
9
ns
2.
t
ADH
Address Strobe Hold Time
3
3
3
ns
3.
t
SU
Synchronous Input Setup
14
12
9
ns
4.
t
H
Synchronous Input Hold
3
3
3
ns
5.
t
BLSU
BLAST Input Setup
14
12
9
ns
6.
t
BLH
BLAST Input Hold
3
3
3
ns
7.
t
RZH
READY 3-state to Valid Delay Relative to
*
PCLK
29
24
19
ns
8.
t
RHL
READY Synchronous Assertion Delay
26
21
17
ns
9.
t
RLH
READY Synchronous De-assertion Delay
25
20
16
ns
10.
t
RHZ
READY Valid to 3-state Delay Relative to
*
PCLK
27
22
17
ns
11.
t
ARA
Address Input to Row Address Output Delay (Note 1)
23
19
15
ns
12.
t
RAH
*
PCLK or PCLK to Row Address Hold
40
33
26
ns
13.
t
CAV
*
PCLK or PCLK to Column Address Valid (Note 1)
38
31
25
ns
14.
t
CAH
PCLK to Column Address Hold
4
4
4
ns
15.
t
DRAH
DRAM Row Address Hold (Note 2)
t
M-4
t
M-4
t
M-3
ns
16.
t
RSHL
PCLK to RAS Asserted Delay (Note 1)
29
24
19
ns
17.
t
RSLH
PCLK to RAS De-asserted Delay (Note 1)
26
21
17
ns
18.
t
CHL
PCLK to CAS Asserted Delay (Note 1)
23
19
15
ns
19.
t
CLH
PCLK to CAS De-asserted Delay (Note 1)
20
16
13
ns
20.
t
BHL
PCLK to Buffer Control Asserted Delay (Note 1)
26
21
17
ns
21.
t
BLH
PCLK to Buffer Control De-asserted Delay (Note 1)
4
23
4
19
4
15
ns
22.
t
BSV
PCLK to Bank Select Valid Time (Note 1)
26
21
17
ns
23.
t
BSH
PCLK to Bank Select Hold Time (Note 1)
4
4
4
ns
24.
t
WEHL
*
PCLK to Write Enable Asserted Delay (Note 1)
31
25
20
ns
25.
t
WELH
PCLK to Write Enable De-asserted Delay (Note 1)
ns
26.
t
BCAH
*
PCLK to Column Address Hold Time (Burst) (Note 1)
5
5
4
ns
27.
t
BCAV
*
PCLK to Column Address Valid Delay (Burst) (Note 1)
29
23
19
ns
28.
t
LEHL
*
PCLK to Latch Enable Assertion
23
19
15
ns
29.
t
LELH
PCLK to Latch Enable De-assertion
20
16
13
ns
30.
t
RFA
PCLK to Row Address Valid (Refresh)
38
31
25
ns
31.
t
RFH
PCLK to Row Address Hold (Refresh)
5
5
4
ns
32.
t
RFHL
REFRESH Synchronous Assertion Delay
20
16
13
ns
33.
t
RFLH
REFRESH Synchronous De-assertion Delay
20
16
13
ns
*
Signal output delays are measured relative to PCLK (except as indicated) using a 50 pF load.
Note 1:
Derate the given delays by 0.006 ns per pF of load in excess of 50 pF.
Note 2:
t
M
e
PCLK High duration when configuration bit 18
e
0. t
M
e
PCLK cycle time
e
1/
(PCLK frequency)
for configuration bit 18
e
1. Timing for Rev AB
silicon.
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC096 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NSBMC096-16 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
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