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參數(shù)資料
| 型號： | NSBMC025 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Burst Memory Controller(脈沖存儲控制器) |
| 中文描述： | 突發(fā)內(nèi)存控制器（脈沖存儲控制器） |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 266K |
| 代理商： | NSBMC025 |
Timing Parameters
INTERFACE TIMING
The NSBMC096 interface to the i960 CA/CF has been de-
signed for direct interconnect. It is not necessary to place
other Iogic devices between the processor and the
NSBMC096, nor is their use encouraged. The introduction
of intermediate address or control signal buffers can result
in skews or delays that will require the system clock fre-
quency to be derated for operation under worst case condi-
tions. The timing diagrams presented in this section assume
that all signals between the processor and the NSBMC096
are un-buffered.
REFRESH TIMING
Figure 5 details the timing of the RAS only refresh per-
formed by the memory controller when there is a competing
request from a bus master. A competing request is defined
as any request that occurs between T0 and T5. For any
request in this range, the timing is exactly as shown. As
illustrated, the diagram represents the timing that results
when Cycle Extend is disabled. If Cycle Extend is enabled,
an additional cycle is inserted at T3 and T8.
SIMPLE ACCESS TIMING
The NSBMC096 can return data to the processor in only 3
or 4 clock cycles for a basic access (2 or 3 wait states)
depending on whether Cycle Extend is enabled. If multiple
access cycles are requested back to back then the BMC will
pause for a minimum of 2 clocks between RAS cycles to
insure that the RAS pre-charge time is met. This will result in
5 or 6 clocks between successive simple cycles.
Figure 6 shows the timing relationship between the system
clock, processor control signals and NSBMC096 outputs.
AIl NSBMC096 outputs are derived synchronously with the
exception of t
ARA
(processor address to row address de-
lay). Two simple access cycles are shown in the diagram.
The first is a read cycle that assumes that the NSBMC096
was idle prior to the start of the cycle, the second is backed
onto the first to show the effect of RAS pre-charge imposed
by NSBMC096. If Cycle Extend is enabled, a wait state will
be inserted after cycles T3 and T8.
BURST ACCESS TIMING
When a burst access is requested by the processor, the
NSBMC096 generates the sequence in Figure 7. If the burst
is for 2 words (load double for example), the processor gen-
erates
*
BLAST in T5 and the sequence is shortened appro-
priately. The first access of the burst sequence begins in the
same manner as a simple access. Consequently the timing
parameters from Figure 6 may be applied in Figure 7.
TL/V/11805–8
FIGURE 5. Refresh Timing
11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NSBMC096 | Burst Memory Controller(脈沖存儲控制器) |
| NSBMC033 | Burst Memory Controller(脈沖存儲控制器) |
| NSBMC096VF | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096-16 | NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC290-16 | Burst Mode Memory Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSBMC096 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NSBMC096-16 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:NSBMC096-16/-25/-33 Burst Memory Controller |
| NSBMC096VF-16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DRAM Controller |
| NSBMC096VF-25 | 功能描述:IC CONTROLLER BURST MEM 132-PQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 控制器類型:靜態(tài) RAM（SRAM） 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC W 包裝:管件 |
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