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| 型號： | NS32FX16-15 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | FILM/M CAPACITANCE=0.001 VOLT=630 |
| 中文描述： | 影像/信號處理器 |
| 文件頁數(shù)： | 86/88頁 |
| 文件大?。?/td> | 902K |
| 代理商： | NS32FX16-15 |
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Appendix B: Instruction Execution Times
(Continued)
TABLE B-3. Average Instruction Execution Times with No Wait-States
(Continued)
Instruction
Number of Clock Cycles
Notes
BITWT
16
28
28
a
(shift
b
8)
Shift
e
0
Shift
e
1
x
8
Shift
l
8
Shift
e
0
x
8, Pre-Read
Shift
e
0
x
8, No Pre-Read
Shift
l
8, Pre-Read
Shift
l
8, No Pre-Read
EXTBLT
35
a
(19
a
12
*
width )
*
height
35
a
(13
a
12
*
width )
*
height
35
a
(17
a
13
*
width )
*
height
35
a
(11
a
13
*
width )
*
height
MOVMPB,W
16
a
7
*
R2
MOVMPD,W
16
a
8
*
R2
SBITS
39
42
R2
s
25
R2
l
25
SBITP
8
a
(34
*
R2)
TABLE B-4. Average Instruction Execution Times with Wait-States
Instruction
Number of Clock Cycles
Notes
BBOR
42
a
((107
a
2
*
Twaitblt)
a
(44
a
Twaitblt)
*
(width
b
2))
*
height
BBXOR
44
a
((107
a
2
*
Twaitblt)
a
(44
a
Twaitblt)
*
(width
b
2))
*
height
BBAND
45
a
((111
a
2
*
Twaitblt)
a
(44
a
Twaitblt)
*
(width
b
2))
*
height
BBFOR
48
a
((74
a
2
*
Twaitblt)
a
(32
a
Twaitblt)
*
(width
b
2))
*
height
BBSTOD
66
a
((170
a
2
*
Twaitblt)
a
(60
a
Twaitblt)
*
(width
b
2))
*
height
BITWIT
16
a
Twaitrds
a
Twaitrdd
a
Twaitwrd
28
a
Twaitblt
Shift
e
0
Shift
e
1
x
8
EXTBLT
35
a
(19
a
(12
a
(Twaitrds
a
Twaitrdd
a
Twaitwrd) )
*
width )
*
height
35
a
(13
a
(12
a
(Twaitrds
a
Twaitrdd
a
Twaitwrd))
*
width )
*
height
Pre-Read
No Pre-Read
MOVMPB,W
16
a
7
*
R2
a
(Twaitwr
b
1)
*
R2
16
a
7
*
R2
Twaitwr
l
1
Twaitwr
s
1
MOVMPD
16
a
8
*
R2
a
Twaitwr
*
R2
SBITS
39
a
(2
*
Twaitrdd
a
2
*
Twaitwrd
a
2
*
Twaitrds)
42
a
(2
*
Twaitrdd
a
2
*
Twaitrds)
R2
s
25
R2
l
25
SBITP
8
a
(34
*
R2)
a
((Twaitrdd
a
Twaitwrd)
*
R2)
B.3 DSPM INSTRUCTIONS
A DSPM instruction execution starts with the CPU core writ-
ing to the CTL register. The execution time is counted from
state T3 of this transaction until all the results are ready,
either in the accumulator or in the coefficient RAM array.
The execution times, in clock cycles, for the various DSPM
instructions are listed in Table B-5.
It is assumed that External Hold Requests do not occur in
the middle of a VCMAD, VCMUL or VCMAC instruction.
The parameters n and w represent the number of elements
in the vector instruction and the number of wait states ap-
plied to each DSPM bus transaction respectively.
TABLE B-5. DSPM Instruction Execution Times
Instruction
Number of Clock Cycles
VCMAD
VCMUL
VCMAC
VCMAG
9
a
8
*
n
a
2
*
n
*
w
9
a
8
*
n
a
2
*
n
*
w
6
a
8
*
n
a
2
*
n
*
w
5
a
8
*
n
86
相關PDF資料 |
PDF描述 |
|---|---|
| NS32FX16-20 | Imaging/Signal Processor |
| NS32FX16-25 | Imaging/Signal Processor |
| NS32FX164-20 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
| NS32FV16-25 | Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | Advanced Imaging/Communication Signal Processors(高級圖象/通訊信號處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| NS32FX16-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX16-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor |
| NS32FX164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| NS32FX164-20 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
| NS32FX164-25 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors |
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