參數(shù)資料
型號(hào)： NS32FX16-15
廠商： National Semiconductor Corporation
英文描述： FILM/M CAPACITANCE=0.001 VOLT=630
中文描述： 影像/信號(hào)處理器
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文件大?。?/td> 902K
代理商： NS32FX16-15
Appendix B: Instruction Execution Times
(Continued)
B.2 SPECIAL GRAPHICS INSTRUCTIONS
This section provides the execution times for the special
graphics instructions. Table B-3 lists the average instruction
execution times for different shift values and for a no-wait-
state system design. The ‘‘No Option’’ of each instruction is
used. The effect of wait states on the execution time is rath-
er difficult to evaluate due to the pipelined nature of the read
and write operations.
Instructions that have shift amounts, such as BBOR,
BBXOR, BBAND, BBFOR and BITWT, make use of the par-
allel nature of the Series 32000
é
/EP processors by doing
the actualshift during the reading of the double-word desti-
nation data. This means that if there are wait states on read
operations, these instructions are able to shift further, with-
out impacting the overall execution time. For example, the
total execution time for a BBFOR operation, shifting 8 bits,
with 2 wait states on read operations, is the same as for a
BBFOR operationshifting by 12 bits. This is because a des-
tination read takes 4 clock cycles longer than a no-wait-
state double-word read does. Note that this effect is not
valid for more than 4 wait states because at 4 wait states, all
possible shift values (0–15) are ‘‘hidden’’ during the desti-
nation read.
Table B-4 shows the average execution times with wait
states, assuming a shift value of eight unless stated other-
wise. The parameters used in the execution time equations
are defined below.
Twaitrd
The number of wait states applied for a Read
operation.
Twaitr
The number of wait states applied for a Write op-
eration.
Twaitrds
The number of wait states applied for a Read
operation on source data. This also refers to the
number of wait states applied for a table memory
access (in the SBITS instruction, for example).
Twaitrdd
The number of wait states applied for a Read
operation on destination data.
Twaitwrd The number of wait states applied for a Write op-
eration on destination data.
Twaitrds
a
Twaitrdd
*
2
a
Twaitwrd
*
2, the
value used for BITBLT timing.
Twaitbt
width
The width of a BITBLT operation, in words.
height
The height of a BITBLT operation, in scan lines.
shift
The number of bits of shift applied.
B.2.1 Execution Time Calculation for Special Graphics
Instructions
The execution time for a special graphics instruction is ob-
tained by inserting the appropriate parameters to the equa-
tion for that instruction and evaluating it.
For example, to calculate the execution time of the BBOR
instruction applied to a 10-word wide and 5-line high data
block, assuming a shift count of 15 and a no-wait-state sys-
tem, the following equation from Table B-3 is used.
42
a
(107
a
44
*
(width
b
2))
*
height
a
((shift
b
8)
*
width
*
height)
Substituting the appropriate values to the shift, width and
height parameters yields:
45
a
(107
a
44
*
(10
b
2))
*
50
a
((15
b
8)
*
10
*
50)
or
42
a
(107
a
352)
*
50
a
(7
*
500)
e
26,492 clocks or
1.77 ms
@
15 MHz
This represents the ‘‘worst case’’ time for this instruction,
since ashift of greater than 15 bits can be handled by mov-
ing the source and destination pointers by 2 bytes and ad-
justing the shift amount.
The ‘‘best case’’ and ‘‘a(chǎn)verage case’’ times for most in-
structions are the same, due to reading the destination data
during the shifting of the source data.
TABLE B-3. Average Instruction Execution Times with No Wait-States
Instruction
Number of Clock Cycles
Notes
BBOR
42
a
(107
a
44
*
(width
b
2))
*
height
42
a
(107
a
44
*
(width
b
2))
*
height
a
((shift
b
8)
*
width
*
height )
Shift
e
0
x
8
Shift
l
8
BBXOR
44
a
(107
a
44
*
(width
b
2))
*
height
44
a
(107
a
44
*
(width
b
2))
*
height
a
((shift
b
8)
*
width
*
height )
Shift
e
0
x
8
Shift
l
8
BBAND
45
a
(111
a
44
*
(width
b
2))
*
height
45
a
(111
a
44
*
(width
b
2))
*
height
a
((shift
b
8)
*
width
*
height )
Shift
e
0
x
8
Shift
l
8
BBFOR
48
a
(61
a
25
*
(width
b
2))
*
height
48
a
(74
a
32
*
(width
b
2))
*
height
48
a
(74
a
32
*
(width
b
2))
*
height
a
((shift
b
8)
*
width
*
height )
Shift
e
0
Shift
e
1
x
8
Shift
l
8
BBSTOD
66
a
(170
a
60
*
(width
b
2))
*
height
66
a
(170
a
60
*
(width
b
2))
*
height
a
((shift
b
8)
*
width
*
height )
Shift
e
0
x
8
Shift
l
8
85
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