參數(shù)資料
型號(hào)： NS32FX16-15
廠商： National Semiconductor Corporation
英文描述： FILM/M CAPACITANCE=0.001 VOLT=630
中文描述： 影像/信號(hào)處理器
文件頁數(shù)： 42/88頁
文件大小： 902K
代理商： NS32FX16-15
3.0 Functional Description
(Continued)
Tracing is disabled.
Supervisor mode is enabled.
Supervisor stack space is used when the TOS addressing
mode is indicated.
No trace traps are pending.
Only NMI is enabled. Maskable interrupts are disabled.
BPU is inactive high.
The Clock Scaling Factor is set to 1, refer to Section 3.5.3.
Note that vector/non-vectored interrupts have not been se-
lected. While interrupts are disabled, a SETCFG
[
I
]
instruc-
tion must be executed to enable vectored interrupts. If non-
vectored interrupts are required, a SETCFG without the
[
I
]
must be executed.
The presence/absence of the NS32081, NS32181, or
NS32381 has also not been declared. If there is a Floating-
Point Unit, a SETCFG
[
F
]
instruction must be executed. If
there is no floating-point unit, a SETCFG without the
[
F
]
must be executed.
In general, a SETCFG instruction must be executed in the
reset routine, in order to properly configure the CPU. The
options should be combined, and executed in a single in-
struction. For example, to declare vectored interrupts, a
Floating-Point unit installed, and full CPU clock rate, exe-
cute a SETCFG
[
F, I
]
instruction. To declare non-vectored
interrupts, no FPU, and full CPU clock rate, execute a
SETCFG
[ ]
instruction.
3.5.5 Bus Cycles
The NS32FX16 will perform bus cycles for one of the follow-
ing reasons:
1. To fetch instructions from memory.
2. To write or read data to or from memory or external pe-
ripheral devices.
3. To acknowledge an interrupt, or to acknowledge comple-
tion of an interrupt service routine.
4. To notify external logic of any accesses to the on-chip
peripheral device registers or internal RAM.
5. To transfer information to or from a Slave Processor.
3.5.5.1 Bus Status
The NS32FX16 CPU presents four bits of Bus Status infor-
mation on pins ST0–ST3. The various combinations on
these pins indicate why the CPU is performing a bus cycle,
or, if it is idle on the bus, they why it is idle.
The Bus Status pins are interpreted as a 4-bit value, with
ST0 the least significant bit. Their values decode as follows:
0000 D The bus is idle because the CPU does not need to
perform a bus access.
0001 D The bus is idle because the CPU is executing the
WAIT instruction.
0010 D DSP Module Data Transfer.
0011 D The bus is idle because the CPU is waiting for a
Slave Processor to complete an instruction.
0100 D Interrupt Acknowledge, Master
The CPU is performing a Read cycle to acknowl-
edge an interrupt request. See Section 3.2.3.
0101 D Interrupt Acknowledge, Cascaded.
The CPU is reading an interrupt vector to acknowl-
edge a maskable interrupt request from a Cascad-
ed Interrupt Control Unit.
0110 D End of Interrupt, Master.
The CPU is performing a Read cycle to indicate
that it is executing a Return from Interrupt (RETI)
instruction at the completion of an interrupt’s serv-
ice procedure.
0111 D End of Interrupt, Cascaded.
The CPU is performing a read cycle from a Cas-
caded Interrupt Control Unit to indicate that it is
executing a Return from Interrupt (RETI) instruc-
tion at the completion of an interrupt’s service pro-
cedure.
1000 D Sequential Instruction Fetch.
The CPU is reading the next sequential word from
the instruction stream into the Instruction Queue. It
will do so whenever the bus would otherwise be
idle and the queue is not already full.
1001 D Non-Sequential Instruction Fetch
The CPU is performing the first fetch of instruction
code after the Instruction Queue is purged. This
will occur as a result of any jump or branch, any
interrupt or trap, or execution of certain instruc-
tions.
1010 D Data Transfer.
The CPU is reading or writing an operand of an
instruction.
1011 D Read RMW Operand.
The CPU is reading an operand which will subse-
quently be modified and rewritten. The write cycle
of RMW will have a ‘‘write’’ status.
1100 D Read for Effective Address Calculation.
The CPU is reading information from memory in
order to determine the Effective Address of an op-
erand. This will occur whenever an instruction uses
the Memory Relative or External addressing mode.
1101 D Transfer Slave Processor Operand.
The CPU is either transferring an instruction oper-
and to or from a Slave Processor, or it is issuing
the Operation Word of a Slave Processor instruc-
tion.
1110 D Read Slave Processor Status.
The CPU is reading a Status Word from a Slave
Processor after the Slave Processor has signalled
completion of an instruction.
1111 D Broadcast Slave ID.
The CPU is initiating the execution of a Slave Proc-
essor instruction by transferring the first byte of the
instruction, which represents the slave processor
indentification.
3.5.5.2 Basic Read and Write Cycles
The sequence of events occurring during a CPU access to
either memory or peripheral device is shown in Figure 3-21
for a read cycle, and Figure 3-22 for a write cycle.
42
相關(guān)PDF資料
PDF描述
NS32FX16-20 Imaging/Signal Processor
NS32FX16-25 Imaging/Signal Processor
NS32FX164-20 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
NS32FV16-25 Advanced Imaging/Communication Signal Processors
NS32FX164-25 Advanced Imaging/Communication Signal Processors(高級(jí)圖象/通訊信號(hào)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NS32FX16-20 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor
NS32FX16-25 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Imaging/Signal Processor
NS32FX164 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
NS32FX164-20 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
NS32FX164-25 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Imaging/Communication Signal Processors
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