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參數(shù)資料
| 型號(hào)： | NM27P040Q170 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PROM |
| 英文描述： | Inductor; Inductor Type:Standard; Inductance:88uH; Series:CMS; DC Resistance Max:0.01ohm; Package/Case:PCB Surface Mount; Core Material:Ferrite; Current, It rms:3.95A; Leaded Process Compatible:Yes; Leakage Inductance:0.85uH RoHS Compliant: Yes |
| 中文描述： | 512K X 8 UVPROM, 170 ns, CDIP32 |
| 封裝： | WINDOWED, CERAMIC, DIP-32 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 151K |
| 代理商： | NM27P040Q170 |
Capacitance
T
A
e a
25
§
C, f
e
1 MHz (Note 2)
Symbol
Parameter
Conditions
Typ
Max
Units
C
IN
Input Capacitance
V
IN
e
0V
9
15
pF
C
OUT
Output Capacitance
V
OUT
e
0V
12
15
pF
AC Test Conditions
Output Load
1 TTL Gate and
C
L
e
100 pF (Note 8)
Input Rise and Fall Times
s
5 ns
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs
Outputs
0.8V and 2V
0.8V and 2V
AC Waveforms
(Notes 6, 7, and 9)
TL/D/11367–3
Note 1:
Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
b
t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
é
, the measured V
OH1
(DC)
b
0.10V;
Low to TRI-STATE, the measured V
OL1
(DC)
a
0.10V.
Note 5:
TRI-STATE may be attained using OE or CE.
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
m
F ceramic capacitor be used on
every device between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
a
1.0V to avoid latch-up and device damage.
Note 8:
1 TTL Gate: I
OL
e
1.6 mA, I
OH
e b
400
m
A.
C
L
: 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to
b
2.0V for 20 ns Max.
Note 11:
CMOS input: V
IL
e
GND
g
0.3V, V
IH
e
V
CC
g
0.3V.
4
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| NM27P040Q120 | 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
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| NM27P040QE150 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
| NM27P040QE170 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
| NM27P040QM150 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
| NM27P040QM200 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
| NM27P040QXXX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
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