參數(shù)資料
型號(hào): NCP1578MNR2G
廠商: ON Semiconductor
文件頁數(shù): 6/22頁
文件大小: 1861K
描述: IC REG DL BCK/LINEAR SYNC 20-QFN
產(chǎn)品變化通告: Product Obsolescence 19/Dec/2008
標(biāo)準(zhǔn)包裝: 4,000
拓?fù)洌?/td> 降壓(降壓)同步(1),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 2
頻率 - 開關(guān): 300kHz
電壓/電流 - 輸出 1: 控制器
電壓/電流 - 輸出 2: 5V,50mA
帶 LED 驅(qū)動(dòng)器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 4.5 V ~ 24 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 帶卷 (TR)
NCP1578
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS
(V
BAT
 = 12 V, LDO5 = V
CCP
 = 5 V, T
A
 = -40 to 85癈, for min/max values unless otherwise noted. Typical values are at T
A
 = 25_C.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
SUPPLY SECTION
Input Voltage
V
BAT
Single Supply Configuration, See Figure 2
Ext +5 V and V
IN
 Configuration, See Figure 3
6.0
4.5
-
24
V
VBAT Operating Supply Current
I
BAT
LDO5 & SMPS are Enabled, See Figure 2
TG and BG are 3 nF Capacitor Load
V
BAT
 = 12 V
-
2
3
mA
V
BAT
 = LDO5 See Figure 3
TG and BG are 3 nF Capacitor Load
V
BAT
 = 5 V
-
-
3
mA
VBAT Shutdown Current
I
BATSD
V
BAT
 = 6 V to 24 V, EN_LDO = 0 V,
EN_SW = 0 V
-
10
30
mA
UNDERVOLTAGE MONITOR
LDO5 UVLO Lower Threshold
VLDO5UV-
Falling Edge
-
4.1
-
V
LDO5 Undervoltage Lockout
Hysteresis
VLDO5UVHYS
-
330
-
mV
LINEAR REGULATOR
LDO5 Input Voltage Range
LDO5_IN
V
BAT
 = LDO5 for 5 V Configuration See
Figure 3
4.5
5.0
5.5
V
LDO5 Output Voltage
LDO5
V
BAT
 = 6 V to 24 V, EN_LDO > 1.4 V, I
LDO5
 =
0 to 50 mA
4.85
5.0
5.15
V
LDO5 Maximum Output Current
I
LDO5_MAX
V
BAT
 = 6 V to 24 V, EN_LDO > 1.4 V
50
-
-
mA
SMPS CONTROLLERS
FB Feedback Voltage, Control Loop
in Regulation
V
FB
T
A
 = 25癈
T
A
 = -40 to 85癈
0.792
0.788
0.8
0.8
0.808
0.812
V
Operating Frequency
F
SW
270
300
330
kHz
Ramp Amplitude
V
RAMP
VOCSET = 12 V (Note 3)
-
1.02
-
V
Ramp Amplitude to VIN Ratio
DVRAMP/DVIN
VOCSET = 4.5 V to 24 V (Note 3)
-
83
-
mV/V
Minimum Duty Cycle
D
min
-
-
0
%
Maximum Duty Cycle
D
max
VOCSET = 4.5 V to 24 V
90
-
-
%
Voltage Error Amplifier DC Gain
Gain
(Note 3)
-
70
-
dB
Error Amplifier Unity Gain Bandwidth
Ft
COMP to GND = 100 pF,
1.0 W in Series (Note 3)
-
2
-
MHz
Voltage Error Amplifier Slew Rate
SR
(Note 3)
-
3.0
-
V/靤
OCSET Pin Current Sink
I
OC
OCSET = 4.0 V
34
40
50
mA
OCSET Pin Current Sink
Temperature Coefficient
TC
IOC
3200
ppm/癈
TG Gate Driver Pull-High
Resistance
R
H_TG
V
BST
 - V
SWN
 = 5 V, V
TG
 - V
SWN
 = 4 V
-
1.5
4.0
W
TG Gate Driver Pull-Low Resistance
R
L_TG
V
BST
 - V
SWN
 = 5 V, V
TG
 - V
SWN
 = 1 V
-
1.5
4.0
W
BG Gate Driver Pull-High
Resistance
R
H_BG
V
CCP
 = 5 V, V
BG
 = 4 V
-
1.5
4.0
W
BG Gate Driver Pull-Low Resistance
R
L_BG
V
CCP
 = 5 V, V
BG
 = 1 V
-
0.9
3.0
W
Soft-start Current
I
ss
EN_SW = 5.0 V; Vss = 0 V
2.8
4.0
5.2
mA
PGDLY Delay Current
I
PG_DLY
EN_SW = 5.0 V, V
PG_DLY
 = 0 V
1.4
2.0
2.6
mA
PGDLY Threshold
Vth
PG_DLY
-
1.25
-
V
3. Guaranteed by design, not tested in production.
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