參數(shù)資料
型號(hào)： NCP1578MNR2G
廠商： ON Semiconductor
文件頁(yè)數(shù)： 19/22頁(yè)
文件大?。?/td> 1861K
描述： IC REG DL BCK/LINEAR SYNC 20-QFN
產(chǎn)品變化通告： Product Obsolescence 19/Dec/2008
標(biāo)準(zhǔn)包裝： 4,000
拓?fù)洌?/td> 降壓（降壓）同步（1），線性（LDO）（1）
功能： 任何功能
輸出數(shù)： 2
頻率 - 開(kāi)關(guān)： 300kHz
電壓/電流 - 輸出 1： 控制器
電壓/電流 - 輸出 2： 5V，50mA
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 4.5 V ~ 24 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-QFN（4x4）
包裝： 帶卷 (TR)
NCP1578
http://onsemi.com
19
undershoot DV
-
 due to load step up DI can be estimated by
the following equation:
DV
*
+DI ESR)
DI
C
out
 
I*
V
o
V
in
F
S
(eq. 11)
and the voltage overshoot DV
+
  due to load release can be
estimated by the following equation:
DV
)
+
L I
o
)
DI
L
2
2
)C
out
 V
2
o
C
out
*V
OUT
(eq. 12)
Where:
I
O
 = Load current step
Other parameters for selection of output capacitor are the
voltage rating and ripple current rating. In general, the
voltage rating should be at least 1.25 times the output
voltage and the RMS ripple current rating should be greater
then the inductor ripple current.
Output Inductor Selection
Basically, a physical inductor can be simply modeled as
two components: an ideal inductance L and an ideal resistor
DCR. The value of L determines the output ripple voltage,
inductor ripple current and performance of load transients.
And DCR contributes the system loss. Hence, the higher the
DCR, the lower the efficiency of the system will be.
In general, the typical inductor ripple current is 30% of the
maximum load current. So based on this criteria, by simple
rearrangement of Equation 10, the required inductance can
be estimated as follow:-
Lw
V
in
*V
o
 V
o
0.3 I
O(max)
 V
in
 F
S
(eq. 13)
Where:
I
O(max)
 = Maximum load current
In addition, The DC current rating of the inductor should
be about 1.2 times of the peak inductor current at maximum
output load current and in order to achieve the good system
efficiency, DCR should be minimized. In general, inductor
with about 2 mW to 3 mW per mH should be used. In some
cases, larger inductor value can be selected to achieve higher
efficiency as long as it still meets the required voltage
overshoot at load release and inductor DC current rating.
MOSFET Selection
For selection of MOSFET, gate drive voltage (V
GS
),
ON-Resistance (R
DSON
), gate input capacitance (C
GS
) and
gate charges (Q
G
, Q
GD
 and Q
GS
) are the key parameters to
be considered.
For ON-resistance, in consideration of efficiency and
power dissipation, it should be the lower the better. In
general, for the buck converter, the R
DSON
 of low side
MOSFET is usually lower than that of high side MOSFET.
It is because the switching on time of lower side MOSFET
is longer than that of high side MOSFET especially at the
high V
in
 and low V
o
 case. For practical application, high side
MOSFET and low side MOSFET with RDSON about
7.0 mW and 5.0 mW respectively can achieve good
efficiency.
In order to have better immunity to low side MOSFET
false switching on due to high dV/dt switching slew rate of
the high side MOSFET, the low side MOSFET should be
selected such that the ratio Q
GD
/Q
GS
 should be low enough.
Overcurrent Protection Component Selection
The overcurrent protection will trip when a peak inductor
current hit the I
LIM
 which is determined by the equation:-
IsubsLIM+
R
OC
 I
OC
R
DS(on)_HS
(eq. 14)
Where:
R
OC
 = Resistor across OCSET pin and V
in
I
OC
 = Constant current flowing into the OCSET pin
R
DS(on)_HS
 = On resistance of the high side MOSFET
Since I
OC
 is varying with device to device and high side
MOSFET's R
DS(on)
 varies with temperature, so in order to
prevent from mis-triggering the over current protection in
normal operating condition, R
OC
 should be determined
based on the following corner conditions:-
1.The minimum I
OC
 value from the electrical table.
2.The maximum high side MOSFET's R
DS(on)
 used
at the highest junction temperature.
3.Estimate I
LIM
 such that I
LIM
 > I
o_max
 + DI
L
/2
where I
o_max
 = Maximum output current rating,
DI
L
 = Inductor ripple current.
In addition, a decoupling capacitor Coc should be added in
parallel with R
OC
 for noise filtering purpose.
PCB Layout Guidelines
The following items should be considered when preparing
PCB layout:
1.All high current traces should be kept as short and
wide as possible to reduce power loss. For
example the input voltage terminal to the drain of
high-side MOSFET, trace from inductor to the
output terminal, etc. Power handling and heat
sinking capability of power traces can be improved
by multiple trace routing at different layer and join
them together with multiple vias.
2.Power components which include the input
capacitor, MOSFETs, inductor and output
capacitor must be placed close together to
minimize the current loop.
3.The thermal pad of the QFN20 package should be
connected to the ground planes for providing good
heat dissipation. It is recommended to use PCB
with 1 oz or 2 oz copper foil. The thermal pad can
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