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參數(shù)資料
| 型號(hào)： | NCP1578MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 14/22頁 |
| 文件大小： | 1861K |
| 描述： | IC REG DL BCK/LINEAR SYNC 20-QFN |
| 產(chǎn)品變化通告： | Product Obsolescence 19/Dec/2008 |
| 標(biāo)準(zhǔn)包裝： | 4,000 |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 300kHz |
| 電壓/電流 - 輸出 1： | 控制器 |
| 電壓/電流 - 輸出 2： | 5V，50mA |
| 帶 LED 驅(qū)動(dòng)器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 4.5 V ~ 24 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 帶卷 (TR) |
NCP1578
http://onsemi.com
14
SMPS is disabled by EN_SW. Note that the PGOOD pin is
valid providing LDO5 is high enough to maintain the
internal logic state.
Overvoltage Protection
When SMPS output voltage is above 115% (typ) the
preset nominal regulation voltage for 16 consecutive
internal clock cycles, the SMPS output will be latch off and
it can be restarted by toggling EN_SW or LDO5.
Undervoltage Protection
When SMPS output falls below 65% (typ) of the nominal
regulation voltage for 16 consecutive internal clock cycles,
the undervoltage fault is set, the SMPS is latched off.
Cycling EN_SW or LDO5 can reset the undervoltage fault
latch and restart the controller.
Soft-Start
The switcher V
OUT
soft-start feature is incorporated in
the device to prevent surge current from power supply and
output voltage overshot during power up. When EN_SW,
LDO5 rises above their respective upper threshold voltages,
the external soft start capacitor C
ss
is charged by a constant
current source I
ss
. When the soft-start voltage reaches the
V
ref
voltage, the soft start process is finished. The soft-start
time Tss can be programmed by the soft-start capacitor
according to the following equation: T
ss
[ (0.8 x C
ss
) / I
ss
.
OPERATION TABLE 1 (Single Supply V
BAT
Configuration)
Input Condition
Operating Condition
Output Condition
FPWM
EN_LDO
EN_SW
SMPS
LDO5
PGOOD
X
Low
X
Off
Off
H-Z
X
High
Low
Off
On
Low
High
High
High
On (FPWM)
On
H-Z
Low
High
High
On (DCM or Pulse Skipping)
On
H-Z
OPERATION TABLE 2 (External +5 V and V
IN
Configuration (Note 4))
Input Condition
Operating Condition
Output Condition
FPWM
EN_LDO
(Note 5)
EN_SW
SMPS
PGOOD
X
Low
Low
Off
Low
High
Low
High
On (FPWM)
H-Z
Low
Low
High
On (DCM or pulse skipping)
H-Z
4. External +5 V is connecting to V
BAT
and LDO5 pin.
5. For this configuration, it is recommended to pull EN_LDO to GND at any time.
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