參數(shù)資料
型號: NCP1578MNR2G
廠商: ON Semiconductor
文件頁數(shù): 17/22頁
文件大?。?/td> 1861K
描述: IC REG DL BCK/LINEAR SYNC 20-QFN
產(chǎn)品變化通告: Product Obsolescence 19/Dec/2008
標準包裝: 4,000
拓撲: 降壓(降壓)同步(1),線性(LDO)(1)
功能: 任何功能
輸出數(shù): 2
頻率 - 開關(guān): 300kHz
電壓/電流 - 輸出 1: 控制器
電壓/電流 - 輸出 2: 5V,50mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 4.5 V ~ 24 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 帶卷 (TR)
NCP1578
http://onsemi.com
17
GENERAL APPLICATION INFORMATION
Introduction
Figure 35 depicts the general control blocks of voltage
mode control loop for a synchronous-rectified buck
converter. The voltage output V
out
 is regulated to a reference
level which is basically governed by the following formula
V
out
+
1)
R1
R2
 V
FB
(eq. 1)
In order to provide proper regulation, the error amplifier is
compared with the internal reference voltage and the output
of the error amplifier is used to provide pulse-width
modulated (PWM) wave.
Loop Compensation
Since NCP1578 is a voltage mode PWM controller with
LC output filter, type III compensation network is
recommended to provide the good closed loop bandwidth
and phase boot with stability under any circumstances. The
purpose of compensation is to obtain a stable close loop
system with the highest possible bandwidth. In another
word, we need to obtain a fast and stable system.
TG
SWN
BG
VOUT
PGND
COMP
FB
PWM Logic
Gate Driver &
Ramp Generator
Vref
A
Error
Amp
Q1
Q2
VIN
CIN
L
DCR
ESR
COUT
R1
R2
R4
C3
C1
C2
R3
NCP1578
Output
Filter
Compensation
Network
Modulator
Figure 35. Buck Converter with Modulator, Output Filter and Compensation Network
Equations Involved in Compensation Network
The following equations are provided as general
guidelines for defining the positions of poles and zeros of the
compensation network.
Output Filter Break Frequency
F
LC
+
1
2p L C
out
(LCDoublePole)
(eq. 2)
F
ESR
+
1
2p ESR C
out
(ESRZero)
(eq. 3)
Compensation Network Break Frequency
F
Z1
+
1
2p R3 C2
(1stZero)
(eq. 4)
F
P1
+
1
2p R3
C1 C2
C1)C2
(1stPole)
(eq. 5)
F
Z2
+
1
2p (R1)R4) C3
(2ndZero) (eq. 6)
F
P2
+
1
2p R4 C3
(2ndPole)
(eq. 7)
Guidelines for selecting compensation component
1.Select a value of R1 between 2 kW and 5 kW
2.Target for close loop bandwidth should be less
than 50% of switching frequency
3.Place 1
st
 zero at 50% of filter double pole.
4.Place 1
st
 pole at ESR zero
5.Place 2
nd
 zero at filter double pole
6.Place 2
nd
 pole at half the switching frequency.
Figure 36 shows an asymptotic plot of the converter gain
against frequency. It gives the general trend of how system
and its individual components behave. Actually, the
Modulator and Filter Gain has a high peak due to the high Q
factor of the output filter. The Open Loop Error Amplifier
Gain bounds the Compensation Gain. The Converter Gain
is constructed on the graph by summing up the Modulator
and Filter Gain (in dB) and the Compensation Gain (in dB).
The Compensation Gain uses the external impedance
network (R1, R4, C3, C1, C2, R3 at Figure 35) to provide a
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