參數(shù)資料
型號(hào)： NCN6004AFTBR2
廠商： ON SEMICONDUCTOR
元件分類： 其它接口
英文描述： Dual SAM/SIM Interface Integrated Circuit
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 6/40頁(yè)
文件大小： 329K
代理商： NCN6004AFTBR2
NCN6004A
http://onsemi.com
6
PIN DESCRIPTION
(continued)
Pin
Description
Type
Symbol
17
C4_B
INPUT
This pin controls the card #B C4 contact. The signal can be either de -multiplexed,
at MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic
state.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is con-
nected to V
, (regardless of the logic state of EN_RPU), and the access to card B
takes place by C4_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or discon-
nected when EN_RPU = Low.
18
RESET_B
INPUT
The signal present on this pin is translated to the RST pin of the external smart card
#B. The CS signal must be Low to valid the RESET function, regardless of the se-
lected card. Assuming the P provides two independent lines to control the RESET
pins, and MUX_MODE = Low, the NCN6004A can control two cards simultaneously.
When MUX_MODE = High, this pin is internally disable, a pull up resistor is con-
nected to V
CC
, (regardless of the logic state of EN_RPU), and the access to card B
takes place by RESET_A associated with CARD_SEL selection bit.
The associated pull up resistor is either connected to V
CC
(EN_RPU = H) or discon-
nected when EN_RPU = Low.
19
I/O_B
INPUT/OUTPUT
This pin carries the data transmission between an external microcontroller and the
external smart card #B.
A built-in bi-directional level translator adapts the signal flowing between the card
and the MCU. The level translator is enabled when CS = Low. The signal present on
this pin is latched when CS = High. Since a dedicated line is used to communicate
the data between the P and the smart card, (assuming MUX_MODE = Low) the
user can activate the two channels simultaneously, assuming the P provides a pair
of I/O lines. When MUX_MODE = High, this pin is internally disable, the pull up re-
sistor is connected to V
, (regardless of the logic state of EN_RPU), and the ac-
cess to card B takes place by I/O_A associated with CARD_SEL selection bit.
20
CRD_DET_A
INPUT
This pin senses the signal coming from the external smart card connector to detect
the presence of card #A. The polarity of the signal is programmable as Normally
Open or Normally Close switch. The logic signal will be activated when the level is
either Low or High, with respect to the polarity defined previously. By default, the
input is Normally Open. A built-in circuit prevents uncontrolled short pulses to gen-
erate an INT signal. The digital filter eliminates pulse width below 50 s (see spec).
21
CRD_C8_A
OUTPUT
This pin controls the card #A C8 contact, according to the ISO7816 specifications. A
built-in level shifter is used to adapt the card and the C, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL =L, or CS = H or
PGM = L, and resume to a transparent mode when card #A is selected and operates
in the transfer mode.The pin is hardwired to zero, the bias being provided by the
V
CC
supply, when either the V
CC
voltage drops below 2.7 V, or during the
CRD_VCC_A start-up time.
22
CRD_C4_A
OUTPUT
This pin controls the card #A C4 contact, according to the ISO7816 specifications. A
built-in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = L, or CS = H, or
PGM = L, and resume to a transparent mode when card #A is selected and operates
in the transfer mode.
The pin is hardwired to zero, the bias being provided by the V
supply, when either
the V
CC
voltage drops below 2.7 V, or during the CRD_VCC_A start-up time.
23
CRD_RST_A
OUTPUT
This pin is connected to the external smart card #A to support the RESET signal. A
built-in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.
The signal present at this pin is latched upon either CARD_SEL = Low, or when CS
or PGM returns to a High, and resume to a transparent mode when card #A is se-
lected. The pin is hardwired to zero, the bias being provided by the V
supply,
when either the V
CC
voltage drops below 2.7 V, or during the CRD_VCC_A start-up
time.
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