參數(shù)資料
型號(hào)： NCN6004AFTBR2
廠商： ON SEMICONDUCTOR
元件分類： 其它接口
英文描述： Dual SAM/SIM Interface Integrated Circuit
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP48
封裝： PLASTIC, TQFP-48
文件頁(yè)數(shù)： 38/40頁(yè)
文件大小： 329K
代理商： NCN6004AFTBR2
NCN6004A
http://onsemi.com
38
PIN FUNCTIONS AND DESCRIPTION
POWER SUPPLY SECTION
DIGITAL INPUT SECTION @ 2.70 < V
CC
< 5.50V,
Normal Operating Mode
CARD INTERFACE SECTION @ 2.70 < V
CC
< 5.50V,
Normal Operating Mode
. . . . . . . . . . . . . . . . . . .
DIGITAL DYNAMIC SECTION NORMAL OPERATING
MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIGITAL DYNAMIC SECTION PROGRAMMING MODE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROGRAMMING AND STATUS FUNCTIONS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYSTEM STATES UPON START UP
PARALLEL/MULTIPLEXED OPERATION MODES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CARD POWER SUPPLY TIMING
POWER DOWN OPERATION
CARD DETECTION
. . . . . . . . . . . . . . . . . . . . . . .
POWER MANAGEMENT
. . . . . . . . . . . . . . . . . .
OUTPUT VOLTAGE PROGRAMMING
DC/DC CONVERTER
. . . . . . . . . . . . . . . . . . . . . .
CLOCK DIVIDER
. . . . . . . . . . . . . . . . . . . . . . . . .
PARALLEL OPERATION
. . . . . . . . . . . . . . . . . .
DATA I/O LEVEL SHIFTER
ESD PROTECTION
. . . . . . . . . . . . . . . . . . . . . . .
SECURITY FEATURES
. . . . . . . . . . . . . . . . . . . .
TEST BOARD SCHEMATIC DIAGRAM
Figures
Figure 1: Pin Diagram
. . . . . . . . . . . . . . . . . . . .
Figure 2: Typical Applications
Figure 3: Block Diagram
. . . . . . . . . . . . . . . . . .
Figure 4: Programming Sequence
Figure 5: Reading ANLG_VCC Status
Figure 6: Simplified MUX_MODE Logic and
Multiplex CIrcuit
. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7: Card Power Supply Turn ON and
Shut OFF Typical Sequence
Figure 8: Card Power Down Sequence
Figure 9: Power Down Sequence
Figure 10: Power Down Sequence: Timing Details
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11: Typical Interrupt Sequence
Figure 12: Card Power Supply Controls
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13: Power On Sequence Timing
Figure 14: Power On and CARD_SEL Sequence
Timings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 15: Basic DC/DC Converter Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16: Theoretical DC/DC Operating
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
10
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11
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12
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16
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27
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34
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2
2
3
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16
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17
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19
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19
20
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21
22
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22
23
24
Figure 17: Typical CRD_VCC Ripple Voltage
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 18: Typical Card Voltage Turn ON and Start-up
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 19: Typical Card Supply Turn OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20: CRD_VCC Efficiency as a Function of the
Input Supply Voltage
. . . . . . . . . . . . . . . . . . . . .
Figure 21: Typical Output Voltage Ripple
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22: Output Current Limit
Figure 23: Output Current Limit as a Function of the
Temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24: Simplified Frequency Divider and
Programming Functions
. . . . . . . . . . . . . . . . . .
Figure 25: Clock Programming Timing
s
Figure 26: Card Clock
Divider Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27: Clock Divider: 8 to 1 Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28: Clock Divider Timing Details
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 29: Clock Divider: Run to Stop High Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 29: Typical Rise and Fall Time in Fast and Slow
Operating Mode
. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 30: Parallel Operation Wiring
MUX_MODE = High
. . . . . . . . . . . . . . . . . . . . . . .
Figure 31: Multiplexed Operation Wiring
MUX_MODE = Low
. . . . . . . . . . . . . . . . . . . . . . .
Figure 32: Dual Bi-directional I/O line Level Shifter
and Multiplex
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 33: Typical I/O Rise and Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34: Test Board Schematic Diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35: Demo Board PCB Top Overlay
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37: Demo Board PCB Top Layer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 38: Demo Board PCB Bottom Layer
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 1 :Programming and Reading Basic Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2: Programming Functions
Table 3: Status Pins Data
. . . . . . . . . . . . . . . . .
Table 4: Operating Conditions Upon Start-up
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5: Card Detection Polarity
Table 6: Ceramic/Electrolytic Capacitors Comparison
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7: Programming Clock Routing
Table 8: Output Clock Slope Selection
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26
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26
27
28
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28
29
29
29
30
30
31
31
32
33
34
36
37
14
15
16
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16
20
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24
30
30
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. . . . .
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