參數(shù)資料
型號(hào)： NAND01GR3A2AZA6
廠商： STMICROELECTRONICS
元件分類(lèi)： PROM
英文描述： 128M X 8 FLASH 1.8V PROM, 15000 ns, PBGA63
封裝： 8.50 X 15 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, TFBGA-63
文件頁(yè)數(shù)： 8/56頁(yè)
文件大?。?/td> 871K
代理商： NAND01GR3A2AZA6
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
16/56
SIGNAL DESCRIPTIONS
See
and
3., Signal Names, for a brief overview of the sig-
nals connected to this device.
Inputs/Outputs (I/O0-I/O7). Input/Outputs 0 to 7
are used to input the selected address, output the
data during a Read operation or input a command
or data during a Write operation. The inputs are
latched on the rising edge of Write Enable. I/O0-I/
O7 are left floating when the device is deselected
or the outputs are disabled.
Inputs/Outputs (I/O8-I/O15). Input/Outputs 8 to
15 are only available in x16 devices. They are
used to output the data during a Read operation or
input data during a Write operation. Command and
Address Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write
Enable. I/O8-I/O15 are left floating when the de-
vice is deselected or the outputs are disabled.
Address Latch Enable (AL). The Address Latch
Enable activates the latching of the Address inputs
in the Command Interface. When AL is high, the
inputs are latched on the rising edge of Write En-
able.
Command Latch Enable (CL). The
Command
Latch Enable activates the latching of the Com-
mand inputs in the Command Interface. When CL
is high, the inputs are latched on the rising edge of
Write Enable.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. When Chip Enable is
low, VIL, the device is selected. If Chip Enable
goes high, vIH, while the device is busy, the device
remains selected and does not go into standby
mode.
When the device is executing a Sequential Row
Read operation, Chip Enable must be held low
(from the second page read onwards) during the
time that the device is busy (tBLBH1). If Chip En-
able goes high during tBLBH1 the operation is
aborted.
Read Enable (R). The Read Enable, R, controls
the sequential data output during Read opera-
tions. Data is valid tRLQV after the falling edge of R.
The falling edge of R also increments the internal
column address counter by one.
Write Enable (W). The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched on the rising edge of Write En-
able.
During power-up and power-down a recovery time
of 1s (min) is required before the Command Inter-
face is ready to accept a command. It is recom-
mended to keep Write Enable high during the
recovery time.
Write Protect (WP). The Write Protect pin is an
input that gives a hardware protection against un-
wanted program or erase operations. When Write
Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin
Low, VIL, during power-up and power-down.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the P/E/R Controller is currently active.
When Ready/Busy is Low, VOL, a read, program or
erase operation is in progress. When the operation
completes Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
teristics section for details on how to calculate the
value of the pull-up resistor.
VDD Supply Voltage. VDD provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations (read,
program and erase).
An internal voltage detector disables all functions
whenever VDD is below 2.5V (for 3V devices) or
1.5V (for 1.8V devices) to protect the device from
any involuntary program/erase during power-tran-
sitions.
Each device in a system should have VDD decou-
pled with a 0.1F capacitor. The PCB track widths
should be sufficient to carry the required program
and erase currents
VSS Ground. Ground, VSS, is the reference for
the power supply. It must be connected to the sys-
tem ground.
相關(guān)PDF資料
PDF描述
NAND01GR4B2BZA1F 64M X 16 FLASH 1.8V PROM, 25000 ns, PBGA63
NAND08GR4B3AZB6 512M X 16 FLASH 1.8V PROM, 25000 ns, PBGA63
NAND256W4A2AZA6E 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55
NCP303LSN41T1 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
NCS6416DWG 8-CHANNEL, VIDEO MULTIPLEXER, PDSO20
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND01GR3A2AZA6E 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND01GR3A2AZA6F 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND01GR3A2AZA6T 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND01GR3A2AZB1 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND01GR3A2AZB1E 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*