參數(shù)資料
型號(hào)： MX805J
英文描述： RF/Baseband Circuit
中文描述： 射頻/基帶電路
文件頁(yè)數(shù)： 22/24頁(yè)
文件大小： 532K
代理商： MX805J
Sub-Audio Signaling Processor
6.1.4
Timing
Timing Parameters for two-way communications between the
μ
C and the MX805A on the C-BUS are shown
in Table 14.
C-BUS Timing
t
CSE
Chip Select Low to First Serial Clock Rising Edge
t
CHS
Last Serial Clock Rising Edge to Chip Select High
t
CSOFF
Chip Select High
t
NXT
Command Data Inter-Byte Time
t
CK
Serial Clock Period
t
CH
Decoder or Encoder Clock High
t
CL
Decoder or Encoder Clock Low
t
CDS
Command Data Set-Up Time
t
CDH
Command Data Hold Time
t
RDS
Reply Data Set-Up Time
t
RDH
Reply Data Hold Time
t
HIZ
Chip Select High to Reply Data High – Z
Table 14: Timing Information
Page 22 of 24
MX805A
2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
All trademarks and service marks are held by their respective companies.
Doc. # 20480116.005
Min.
2.0
4.0
2.0
4.0
2.0
500
500
250
0
250
50.0
Typ.
Max.
2.0
Units
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
ns
ns
ns
ns
μ
s
Notes:
1. Command Data is transmitted to the peripheral MSB (bit 7) first, LSB (bit 0) last. Reply Data is read from
the MX805A MXB (bit 7) first, LSB (bit 0) last.
2. Data is clocked into the MX805A and into the microcontroller on the rising Serial Clock edge.
3. Loaded data instructions are acted upon at the end of each individual, loaded byte.
4. To allow for differing microcontroller serial interface formats, the MX805A will work with either polarity
Serial clock pulses.
CHIP
SELECT
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
ADDRESS/COMMAND
BYTE
FIRST
DATA
BYTE
LAST
DATA
BYTE
FIRST
REPLY
DATA
BYTE
LAST
REPLY
DATA
BYTE
Logic
level
is
not
important
MSB
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
LSB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
t
t
t
CSOFF
t
CSH
HIZ
t
NXT
t
NXT
CK
t
CSE
Figure 10: C-BUS Timing Information
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