參數(shù)資料
型號(hào)： MX29LV320AB
廠商： Macronix International Co., Ltd.
英文描述： 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
中文描述： 32兆位[4米× 8 / 2米× 16]單電壓3V時(shí)僅閃存
文件頁(yè)數(shù)： 12/60頁(yè)
文件大小： 619K
代理商： MX29LV320AB
12
P/N:PM1008
REV. 1.1, MAY 28, 2004
MX29LV320AT/B
OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from
the devices are disabled. This will cause the output pins
to be in a high impedance state.
RESET OPERATION
The RESET pin provides a hardware method of resetting
the device to reading array data. When the RESET pin is
driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET pulse. The
device also resets the internal state machine to reading
array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another
command sequence, to ensure data integrity
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS
±
0.3V, the device draws
CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS
±
0.3V, the standby current will be
greater.
The RESET pin may be tied to system reset circuitry. A
system reset would that also reset the Flash memory,
enabling the system to read the boot-up firm-ware from
the Flash memory.
If RESET is asserted during a program or erase
operation, the RY/BY pin remains a "0" (busy) until the
internal reset operation is complete, which requires a time
of tREADY (during Embedded Algorithms). The system
can thus monitor RY/BY to determine whether the reset
operation is complete. If RESET is asserted when a
program or erase operation is not executing (RY/BY pin
is "1"), the reset operation is completed within a time of
tREADY (not during Embedded Algorithms). The system
can read data tRH after the RESET pin returns to VIH.
Refer to the AC Characteristics tables for RESET
parameters and to Figure 14 for the timing diagram.
SECTOR GROUP PROTECT OPERATION
The MX29LV320AT/B features hardware sector group
protection. This feature will disable both program and
erase operations for these sector group protected. Sec-
tor protection can be implemented via two methods.
The primary method requires VID on the RESET only.
This method can be implemented either in-system or via
programming equipment. This method uses standard
microprocessor bus cycle timing. Refer to Figure 13 for
timing diagram and Figure 14 illustrates the algorithm for
the sector group protection operation.
The alternate method intended only for programming
equipment, must force VID on address pin A9 and con-
trol pin OE, (suggest VID = 12V) A6 = VIL and CE =
VIL(see Table 2). Programming of the protection circuitry
begins on the falling edge of the WE pulse and is termi-
nated on the rising edge. Contact MXIC for details.
To verify programming of the protection circuitry, the pro-
gramming equipment must force V
on address pin A9 (
with CE and OE at VIL and WE at VIH). When A1=1, it
will produce a logical "1" code at device output Q0 for a
protected sector. Otherwise the device will produce 00H
for the unprotected sector. In this mode, the addresses,
except for A1, are don't care. Address locations with
A1= VIL are reserved to read manufacturer and device
codes.(Read Silicon ID)
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECT OPERATION
The MX29LV320AT/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code. It is recommended to protect all sectors before
activating chip unprotect mode.
The primary method requires VID on the RESET only.
This method can be implemented either in-system or via
programming equipment. This method uses standard
microprocessor bus cycle timing. Refer to Figure 13 for
timing diagram and Figure 14 illustrates the algorithm for
the sector group protection operation.
The alternate method intended only for programming
equipment, must force VID on address pin A9 and con-
trol pin OE, (suggest VID = 12V) A6 = VIL and CE =
VIL(see Table 2). Programming of the protection circuitry
begins on the falling edge of the WE pulse and is termi-
nated on the rising edge. Contact MXIC for details.
相關(guān)PDF資料
PDF描述
MX29LV320ABTC-70 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV320ABTC-70G 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV320ABTC-90 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV320ABTC-90G 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
MX29LV320ABTI-70 32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MX29LV320CBTC-90G 制造商:Macronix International Co Ltd 功能描述:NOR Flash, 2M x 16, 40 Pin, Plastic, TSSOP
MX29LV320CBTI-90G 制造商:MACRONIX 功能描述:
MX29LV320DBXEI-70G 制造商:Macronix International Co Ltd 功能描述:MX29LV Series 3 V 32 Mb (4 M x 8) 70 ns Parallel Flash-LFBGA-48
MX29LV320DTTI-70G 制造商:Macronix International Co Ltd 功能描述:2M X 16 FLASH 3V PROM, 70 ns, PDSO48
MX29LV320EBTI-70G 功能描述:IC FLASH PAR 3V 32MB 70NS 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:MX29LV 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:閃存 - NAND 存儲(chǔ)容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*