參數(shù)資料
型號: MVTX2802AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網絡接口
英文描述: Managed 4-Port 1000 Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝: 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù): 50/154頁
文件大小: 1936K
代理商: MVTX2802AG
MVTX2802
Data Sheet
50
Zarlink Semiconductor Inc.
frame.
Bit [4]: End of Transmit CPU Frame indicator. Set before writing the last byte of CPU frame.
Bit [7:5]: Reserved and always write 0’s.
Bit [15:8]: Reserved and write 0’s in 16-bit mode.
11.2.6 Interrupt Register
Interrupt sources (8 bits)
Address = 5 (read only)
When CPU
reads
this register
11.2.7 Control Frame Buffer1 Access Register
11.2.8
Address = 6 (read/write)
When CPU writes to this register, data is written to the Control Command Frame Receive Buffer
When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1
Control Frame Buffer2 Access Register
Address = 7 (read only)
When CPU reads this register, data is read from the Control Command Frame transmit Buffer 2
Indirectly Accessed Registers
11.3 Group 0 Address
11.3.1 MAC Ports Group
11.3.1.1 ECR1Pn: Port N Control Register
I
2
C Address h00+2n; CPU Address:h000+2n (n=0 to 3)
Accessed by CPU, serial interface and I
2
C (R/W)
Bit [0]:
CPU frame interrupt
Bit [1]:
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read
Bit [2]:
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read
Bit [3]
Bit [7:4]:
From any of the gigabit port interrupt
Reserve
Note:
This register is not self-cleared. After reading CPU has to clear the bit writing 0 to it
7
6
5
4
3
2
1
0
Sp State
A-FC
Port Mode
Bit [4:0]
Port Mode
(Default 2’b00)
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