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MVTX2802
Data Sheet
24
Zarlink Semiconductor Inc.
5.3.5 VLAN Port Association Table
VLAN STATUS [2:0]
000:Not a valid entry
001:Blocking status, no RX and TX
010:Not a VLAN member, spanning tree learn status
011:VLAN member, spanning tree learn status
100:Not a VLAN member, spanning tree forward status
101:VLAN member and is subject to aging, spanning tree forward status (Don’t use)
110:VLAN member and is subject to aging, spanning tree forward status
111:VLAN member and is not subject to aging, spanning tree forward status
CPU can create static VLAN port by writing the static status to the VLAN- PORT status entry.
Dynamic VLAN and Port association can be created by writing “110” to the VLAN STATUS. Hardware will age
and refresh the entry based on the VLAN – PORT activity. When the VLAN – PORT is ready to be aged out, a
message is sent to CPU and CPU can remove the VLAN – PORT association by writing “000” to the VLAN
STATUS. As a result, the VLAN and PORT are no long associated and the VLAN domain is shrunk
6.0 Frame Engine
6.1 Data Forwarding Summary
Enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is
moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast,
and its destination port or ports. A VLAN table lookup is performed as well.
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon
receiving a Transmission Scheduling Request, the device will format an entry in the appropriate
Transmission Scheduling Queue (TxSch Q) or Queues. There is 8 transmission queues per Gigabit port,
one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked
list if unicast, or adding an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of
one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality
of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one
logical queue.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of
the destination port.
31
30
29 27
26 0
Valid
Route
Reserved
Port 8 to 0 is VLAN status
Port 8
Port 7
Port 6
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
VLAN
status
Reserved
Reserved
Reserved
Reserved
VLAN
status
VLAN
status
VLAN
status
VLAN
status