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MVTX2802
Data Sheet
29
Zarlink Semiconductor Inc.
Also, when shaping is enabled, it is possible for a P6 queue to explode in length if fed by a greedy source. The
reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet
even if the line is idle. Though we do have global resource management, we do nothing to prevent this situation
locally. We assume SP traffic is policed at a prior stage to the MVTX2802AG.
7.7 WRED Drop Threshold Management Support
To avoid congestion, the Weighted Random Early Detection (WRED) logic drops packets according to specified
parameters. The following table summarizes the behaviour of the WRED logic.
In the table, |Px| is the byte count in queue Px. The WRED logic has three drop levels, depending on the value of N,
which is based on the number of bytes in the priority queues. If delay bound scheduling is used, N equals 16|P7| +
16|P6| + 8|P5| + 4|P4| + 2|P3| + |P2|. If WFQ scheduling is used, N equals |P7| + |P6| + |P5| + |P4| + |P3| + |P2|.
Each drop level has defined high-drop and low-drop percentages, which indicate the percentage of high-drop and
low-drop packets that will be dropped at that level. The X, Y, and Z percent parameters can be programmed using
the registers RDRC0 and RDRC1. Parameters A-F are the byte count thresholds for each priority queue, and are
also programmable. When using delay bound scheduling, the values selected for A-F also control the approximate
bandwidth partition among the traffic classes; see application note.
7.8 Buffer Management
Because the number of frame data buffer (FDB) slots is a scarce resource, and because we want to ensure that
one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we
introduce the concept of buffer management into the MVTX2802AG. Our buffer management scheme is
designed to divide the total buffer space into numerous reserved regions and one shared pool (see Figure 5).
As shown in the figure, the FDB pool is divided into several parts. A reserved region for temporary frames
stores frames prior to receiving a switch response. Such a temporary region is necessary, because when the
frame first enters the MVTX2802AG, its destination port and class are as yet unknown, and so the decision to
drop or not needs to be temporarily postponed. This ensures that every frame can be received first before
subjecting it to the frame drop discipline after classifying.
Six reserved sections, one for each of the highest six priority classes, ensure a programmable number of FDB
slots per class. The lowest two classes do not receive any buffer reservation.
Another segment of the FDB reserves space for each of the 4 Gigabit ports and CPU port. These source port
buffer reservations are programmable. These 9 reserved regions make sure that no well-behaved source port
can be blocked by another misbehaving source port.
P7
P6
P5
P4
P3
P2
High Drop
Low Drop
Level 1
N
≥
240
|P7|
≥
A
KB
|P6|
≥
B
KB
|P5|
≥
C
KB
|P4|
≥
D
KB
|P3|
≥
E
KB
|P2|
≥
F
KB
X%
0%
Level 2
N
≥
280
Y%
Z%
Level 3
N
≥
320
100%
100%
Table 3 - WRED Dropping Scheme