參數(shù)資料
型號(hào)： MTV230M64
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： 8051 Embedded Micro Controller with Flash OSD and ISP
中文描述： 8051嵌入式閃存OSD和ISP的微控制器
文件頁(yè)數(shù)： 8/31頁(yè)
文件大?。?/td> 404K
代理商： MTV230M64
MTV230M64
Page 8 of 31
Reg name
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT4
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT5
PORT6
PORT6
PORT6
addr
F30h(r/w)
F31h(r/w)
F32h(r/w)
F33h(r/w)
F34h(r/w)
F35h(r/w)
F36h(r/w)
F37h(r/w)
F38h(r/w)
F39h(r/w)
F3Ah(r/w)
F3Bh(r/w)
F3Ch(r/w)
F3Dh(r/w)
F3Eh(r/w)
F3Fh(r/w)
F28h(w)
F29h(w)
F2Ah(w)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P40
P41
P42
P43
P44
P45
P46
P47
P50
P51
P52
P53
P54
P55
P56
P57
P60
P61
P62
PORT4
(r/w) :
Port 4 data input/output value.
PORT5
(r/w) :
Port 5 data input/output value.
PORT6
(w) :
Port 6 data output value.
5. PWM DAC
Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of PWM
clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253 or 256,
selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output. If
DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing 00H to DAC
register generates stable low output.
Reg name
DA0
DA1
DA2
DA3
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
F20h (r/w)
F21h (r/w)
F22h (r/w)
F23h (r/w)
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
DA0-3
(r/w) :
* All of PWM DAC converters are centered with value 80h after power on.
The output pulse width control for DA0-3.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC inputs
presence check, frequency counting, polarity detection and H/V output polarity control. The present and
frequency function block treat any pulse shorter than one OSC period as noise.
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