MTV230M64
Page 17 of 31
x = don’t care
AAAAAAAA = Code_address[15:8]
AAAAAAA = OSD_address[13:7]
RRRRRRRR = CRC_register[15:8]
dddddddd-dddddddd = Code_data
ccccc = 10100
→
Program
ccccc = 00110
→
Page Erase 512 bytes or 256 words (Erase)
ccccc = 01101
→
Erase entire Flash (Blank)
ccccc = 11010
→
Clear CRC_register (Clr_CRC)
ccccc = 01001
→
Reset MTV230M64 (Reset_CPU)
X = not defined
aaaaaaaa = Code_address[7:0]
aaaaaaa = OSD_address[6:0]
rrrrrrrr = CRC_register[7:0]
dddd-dddddddd = OSD_data
10.1 ISP Command Write
The 2nd byte of “Command Write” can define the operating mode of MTV230M64 in its “Data write” stage, clear
CRC register, or reset MTV230M64. The bit 0 of 2
nd
byte select the target Flash to be operated (1=OSD,
0=Code). The 3rd byte of Command Write defines the page address (A15-8 of Code Flash, A13-7 of OSD
Flash). A Command Write may consist of 1,2 or 3 bytes.
10.2 ISP Command Read
The 2
nd
byte echoes the current command in ISP slave. The 3
rd
and 4
th
byte reflects the current Flash address.
The 5
th
and 6
th
byte reports the CRC result. A Command Read may consist of 2,3,4,5 or 6 bytes.
10.3 ISP Data Write
The 2
nd
byte defines the Flash’s low address (A7-0 for Code, A6-0 for OSD). After receiving the 3
rd
byte, the
MTV230M64 will execute a Program/Erase/Blank command depends on the preceding “Command Write”. If
Code area is select, the Code Flash’s low address will increase every time when ISP slave acknowledges the
data byte. If OSD Flash is selected, the OSD Flash’s low address will increase every 2 data bytes received. The
Blank/Erase command need one data byte (content is “don’t care”). The executing time is 10mS. During the
10mS period, the ISP slave won’t accept any command/data and returns non-ack to any IIC bus activity. The
Program command may have 1-256 data byte for Code Flash, and have 1-128 word(256 byte) for OSD Flash.
The program cycle time is 60us. If the ISP slave can’t complete the program cycle in time, it will return non-ack
to the following data byte. In the meantime, the low address won’t increase and the CRC won’t count the non-
acked data byte. A Data Write may consist of 1,2 or more bytes.
Data Write (Blank/Erase)
S-tttttt00k-aaaaaaaak-ddddddddk-P ... S-ttttttxxk-
|----Min. 10mS----|
Data Write (Program)
S-tttttt00k-aaaaaaaak-ddddddddk-ddddddddk- ...
|Min. 60uS|
10.4 ISP Data Read
The 1
st
and 2
nd
byte are the same as “Data write” to define the Flash’s low address. Between 2
nd
and 3
rd
byte,
the ISP host may issue Stop-Start or only Re-Start. From the 4
th
byte, the ISP slave send Flash’s data byte/word
to ISP Host. The low address auto increase every time when data byte/word transferred.
10.5 Cyclic Redundancy Check (CRC)
To shorten the verify time, the ISP slave provide a simple way to check if data error occurs during the program
data transfer. After the ISP Host send a lot of data byte to ISP slave, Host can use Command Read to check
CRC register’s result instead of reading every byte in Flash. The CRC register counts every data byte which ISP
slave acknowledges during “Data Write” period. However, the low address byte and the data byte of
Erase/Blank are not counted. The Clear CRC command will write all “1” to the 16-bit CRC register. The OSD
Flash and Code share the same CRC counter. For CRC generation, the 16-bit CRC register is seeded with all
“1” pattern (by device reset or Clear CRC command). The data byte shifted into the CRC register is Msb first.
The real implementation is described as follows:
CRCin = CRC[15]^DATAin;