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參數(shù)資料
| 型號： | MTV230M64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Micro Controller with Flash OSD and ISP |
| 中文描述： | 8051嵌入式閃存OSD和ISP的微控制器 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大小： | 404K |
| 代理商： | MTV230M64 |
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MTV230M64
Page 14 of 31
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
F06h (r)
F06h (w)
F07h (w)
F08h (r)
F08h (w)
F09h (w)
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
ENSlvA
ENSlvB
IICCTR
(r/w) : IIC interface control register.
MAckO = 1
= 0
S, P
=
↑
, 0
= X,
↑
= 1, X
→
In master receive mode, NACK is returned by MTV230M64.
→
In master receive mode, ACK is returned by MTV230M64.
→
Start condition when Master IIC is not during transfer.
→
Stop condition when Master IIC is not during transfer.
→
Will resume transfer after a read/write MBUF operation.
IICSTUS
(r) :
IIC interface status register.
WadrB = 1
→
The data in RCBBUF is word address.
WadrA = 1
→
The data in RCABUF is word address.
SlvRWB = 1
→
Current transfer is slave transmit
= 0
→
Current transfer is slave receive
SAckIn = 1
→
The external IIC host respond NACK.
SLVS
= 1
→
The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1
→
Master IIC bus error, no ACK received from the slave IIC device.
= 0
→
ACK received from the slave IIC device.
INTFLG
(w) :
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this
register while serve the interrupt routine.
SlvBMI = 1
→
No action.
= 0
→
Clear SlvBMI flag.
SlvAMI = 1
→
No action.
= 0
→
Clear SlvAMI flag.
MbufI
= 1
→
No action.
= 0
→
Clear Master IIC bus interrupt flag (MbufI).
INTFLG
(r) :
Interrupt flag.
= 1
= 1
TXBI
RCBI
SlvBMI = 1
TXAI
RCAI
SlvAMI = 1
MbufI
→
Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.
→
Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.
→
Indicates the slave IIC address B match condition.
→
Indicates the TXABUF need a new data byte, clear by writing TXABUF.
→
Indicates the RCABUF has received a new data byte, clear by reading RCABUF.
→
Indicates the slave IIC address A match condition.
→
Indicates a byte is sent/received to/from the master IIC bus.
= 1
= 1
= 1
INTEN
(w) :
Interrupt enable.
ETXBI = 1
ERCBI = 1
ESlvBMI = 1
ETXAI = 1
ERCAI = 1
ESlvAMI = 1
EMbufI = 1
→
Enable TXBBUF interrupt.
→
Enable RCBBUF interrupt.
→
Enable slave address B match interrupt.
→
Enable TXABUF interrupt.
→
Enable RCABUF interrupt.
→
Enable slave address A match interrupt.
→
Enable Master IIC bus interrupt.
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