參數(shù)資料
型號(hào)： MTC20154
廠商： 意法半導(dǎo)體
英文描述： INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
中文描述： 集成ADSL CMOS模擬前端電路
文件頁(yè)數(shù)： 16/21頁(yè)
文件大小： 533K
代理商： MTC20154
MTC20154
16/21
The crystal’s exact oscillation frequency can be tuned around the nominal frequency. This is needed in
order to allow the system to minimize the clock phase shift between the LT and the NT modems. The in-
formation coming from the digital processor via the CTRLIN path is used to drive a 8 bits DAC (resistor
ladder architecture) which generates a control current. This current is externally converted and filtered to
generate the required control voltage for the varicap. The VCXO characteristics are given in the following
table.
Table 20. VCXO characteristics
PLL Based Frequency Doubler
Dual crystal frequency can now be used needed when a 17.644 MHz crystal with the MTC20154 on–board
crystal is used. A frequency doubler, build driver. However, a master clock up around a Phase Locked
Loop (PLL), frequency of 35.328 MHz is still will then be used.
Digital Interface
Control Interface
The digital code setting for the MTC20154 configuration is sent over a serial line (CTRLIN) using the word
clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (’0’), the
three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched
but they are overruled by the normal settings if the TEST pin is low.
Control Interface Timing
The control interface bits are considered valid on each positive edge of the master clock (CLKM). They
will be sampled at this moment. The stop bit will trigger the internal data validation. The timing require-
ments are depicted in the following figure and table:
Figure 9. Control Interface Timing diagram
Data
Min
50
100
-
–
–
–
95
Typical
–
–
8
AVDD/2
–
–
100
Max
–
–
-
–
1.5
4
105
Unity
ppm
ppm
bit
V
LSB
LSB
mA
Needed crystal accuracy
Needed crystal frequency tuning range
DAC resolution
DAC output voltage range
DAC differential non linearity error
DAC integrated non linearity error
VCXO nominal output current
(Rref = 16.5 K AVDD = 3.3 V)
Power consumption
–
.225
–
mW
CLKM
CLKWD
CTRLIN
Start
bit
Th
ctrl data bits
ctrl cmd bits 1 stop bit (high)
Ts
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參數(shù)描述
MTC20154-TQ-C2 制造商:STMicroelectronics 功能描述:
mtc20154-tq-c2tr 制造商:STMicroelectronics 功能描述:
MTC20154-TQ-I1 制造商:STMicroelectronics 功能描述:INTEGRATED ADSL CMOS ANLG FRONT-END CIRCUIT 64TQFP - Tape and Reel
MTC20154TQI1A 功能描述:電信集成電路 ASDL Analg Front End RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray
MTC20154-TQ-I1A 制造商:STMicroelectronics 功能描述:ADSL DMT/ATM IND T - Tape and Reel
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